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[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [arm/] [b.cgs] - Diff between revs 24 and 33

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Rev 24 Rev 33
# arm testcase for b$cond $offset24
# arm testcase for b$cond $offset24
# mach: all
# mach: all
# ??? Still need to test edge cases.
# ??? Still need to test edge cases.
        .include "testutils.inc"
        .include "testutils.inc"
        start
        start
        .global b
        .global b
b:
b:
# b foo
# b foo
        b balways1
        b balways1
        fail
        fail
balways1:
balways1:
# beq foo
# beq foo
        mvi_h_gr r4,4
        mvi_h_gr r4,4
        mvi_h_gr r5,4
        mvi_h_gr r5,4
        cmp r4,r5
        cmp r4,r5
        beq beq1
        beq beq1
        fail
        fail
beq1:
beq1:
        mvi_h_gr r5,5
        mvi_h_gr r5,5
        cmp r4,r5
        cmp r4,r5
        beq beq2
        beq beq2
        b beq3
        b beq3
beq2:
beq2:
        fail
        fail
beq3:
beq3:
# bne foo
# bne foo
        mvi_h_gr r4,4
        mvi_h_gr r4,4
        mvi_h_gr r5,5
        mvi_h_gr r5,5
        cmp r4,r5
        cmp r4,r5
        bne bne1
        bne bne1
        fail
        fail
bne1:
bne1:
        mvi_h_gr r5,4
        mvi_h_gr r5,4
        cmp r4,r5
        cmp r4,r5
        bne bne2
        bne bne2
        b bne3
        b bne3
bne2:
bne2:
        fail
        fail
bne3:
bne3:
# bcs foo
# bcs foo
        mvi_h_cnvz 1,0,0,0
        mvi_h_cnvz 1,0,0,0
        bcs bcs1
        bcs bcs1
        fail
        fail
bcs1:
bcs1:
        mvi_h_cnvz 0,0,0,0
        mvi_h_cnvz 0,0,0,0
        bcs bcs2
        bcs bcs2
        b bcs3
        b bcs3
bcs2:
bcs2:
        fail
        fail
bcs3:
bcs3:
# bcc foo
# bcc foo
        mvi_h_cnvz 0,0,0,0
        mvi_h_cnvz 0,0,0,0
        bcc bcc1
        bcc bcc1
        fail
        fail
bcc1:
bcc1:
        mvi_h_cnvz 1,0,0,0
        mvi_h_cnvz 1,0,0,0
        bcc bcc2
        bcc bcc2
        b bcc3
        b bcc3
bcc2:
bcc2:
        fail
        fail
bcc3:
bcc3:
# bmi foo
# bmi foo
        mvi_h_cnvz 0,1,0,0
        mvi_h_cnvz 0,1,0,0
        bmi bmi1
        bmi bmi1
        fail
        fail
bmi1:
bmi1:
        mvi_h_cnvz 0,0,0,0
        mvi_h_cnvz 0,0,0,0
        bmi bmi2
        bmi bmi2
        b bmi3
        b bmi3
bmi2:
bmi2:
        fail
        fail
bmi3:
bmi3:
# bpl foo
# bpl foo
        mvi_h_cnvz 0,0,0,0
        mvi_h_cnvz 0,0,0,0
        bpl bpl1
        bpl bpl1
        fail
        fail
bpl1:
bpl1:
        mvi_h_cnvz 0,1,0,0
        mvi_h_cnvz 0,1,0,0
        bpl bpl2
        bpl bpl2
        b bpl3
        b bpl3
bpl2:
bpl2:
        fail
        fail
bpl3:
bpl3:
# bvs foo
# bvs foo
        mvi_h_cnvz 0,0,1,0
        mvi_h_cnvz 0,0,1,0
        bvs bvs1
        bvs bvs1
        fail
        fail
bvs1:
bvs1:
        mvi_h_cnvz 0,0,0,0
        mvi_h_cnvz 0,0,0,0
        bvs bvs2
        bvs bvs2
        b bvs3
        b bvs3
bvs2:
bvs2:
        fail
        fail
bvs3:
bvs3:
# bvc foo
# bvc foo
        mvi_h_cnvz 0,0,0,0
        mvi_h_cnvz 0,0,0,0
        bvc bvc1
        bvc bvc1
        fail
        fail
bvc1:
bvc1:
        mvi_h_cnvz 0,0,1,0
        mvi_h_cnvz 0,0,1,0
        bvc bvc2
        bvc bvc2
        b bvc3
        b bvc3
bvc2:
bvc2:
        fail
        fail
bvc3:
bvc3:
# bhi foo
# bhi foo
        mvi_h_gr r4,5
        mvi_h_gr r4,5
        mvi_h_gr r5,4
        mvi_h_gr r5,4
        cmp r4,r5
        cmp r4,r5
        bhi bhi1
        bhi bhi1
        fail
        fail
bhi1:
bhi1:
        mvi_h_gr r5,5
        mvi_h_gr r5,5
        cmp r4,r5
        cmp r4,r5
        bhi bhi2
        bhi bhi2
        b bhi3
        b bhi3
bhi2:
bhi2:
        fail
        fail
bhi3:
bhi3:
        mvi_h_gr r5,6
        mvi_h_gr r5,6
        cmp r4,r5
        cmp r4,r5
        bhi bhi4
        bhi bhi4
        b bhi5
        b bhi5
bhi4:
bhi4:
        fail
        fail
bhi5:
bhi5:
# bls foo
# bls foo
        mvi_h_gr r4,4
        mvi_h_gr r4,4
        mvi_h_gr r5,5
        mvi_h_gr r5,5
        cmp r4,r5
        cmp r4,r5
        bls bls1
        bls bls1
        fail
        fail
bls1:
bls1:
        mvi_h_gr r5,4
        mvi_h_gr r5,4
        cmp r4,r5
        cmp r4,r5
        bls bls2
        bls bls2
        fail
        fail
bls2:
bls2:
        mvi_h_gr r5,3
        mvi_h_gr r5,3
        cmp r4,r5
        cmp r4,r5
        bls bls3
        bls bls3
        b bls4
        b bls4
bls3:
bls3:
        fail
        fail
bls4:
bls4:
# bge foo
# bge foo
        mvi_h_gr r4,4
        mvi_h_gr r4,4
        mvi_h_gr r5,4
        mvi_h_gr r5,4
        cmp r4,r5
        cmp r4,r5
        bge bge1
        bge bge1
        fail
        fail
bge1:
bge1:
        mvi_h_gr r5,3
        mvi_h_gr r5,3
        cmp r4,r5
        cmp r4,r5
        bge bge2
        bge bge2
        fail
        fail
bge2:
bge2:
        mvi_h_gr r5,5
        mvi_h_gr r5,5
        cmp r4,r5
        cmp r4,r5
        bge bge3
        bge bge3
        b bge4
        b bge4
bge3:
bge3:
        fail
        fail
bge4:
bge4:
# blt foo
# blt foo
        mvi_h_gr r4,4
        mvi_h_gr r4,4
        mvi_h_gr r5,5
        mvi_h_gr r5,5
        cmp r4,r5
        cmp r4,r5
        blt blt1
        blt blt1
        fail
        fail
blt1:
blt1:
        mvi_h_gr r5,4
        mvi_h_gr r5,4
        cmp r4,r5
        cmp r4,r5
        blt blt2
        blt blt2
        b blt3
        b blt3
blt2:
blt2:
        fail
        fail
blt3:
blt3:
        mvi_h_gr r5,3
        mvi_h_gr r5,3
        cmp r4,r5
        cmp r4,r5
        blt blt4
        blt blt4
        b blt5
        b blt5
blt4:
blt4:
        fail
        fail
blt5:
blt5:
# bgt foo
# bgt foo
        mvi_h_gr r4,4
        mvi_h_gr r4,4
        mvi_h_gr r5,3
        mvi_h_gr r5,3
        cmp r4,r5
        cmp r4,r5
        bgt bgt1
        bgt bgt1
        fail
        fail
bgt1:
bgt1:
        mvi_h_gr r5,4
        mvi_h_gr r5,4
        cmp r4,r5
        cmp r4,r5
        bgt bgt2
        bgt bgt2
        b bgt3
        b bgt3
bgt2:
bgt2:
        fail
        fail
bgt3:
bgt3:
        mvi_h_gr r5,5
        mvi_h_gr r5,5
        cmp r4,r5
        cmp r4,r5
        bgt bgt4
        bgt bgt4
        b bgt5
        b bgt5
bgt4:
bgt4:
        fail
        fail
bgt5:
bgt5:
# ble foo
# ble foo
        mvi_h_gr r4,4
        mvi_h_gr r4,4
        mvi_h_gr r5,4
        mvi_h_gr r5,4
        cmp r4,r5
        cmp r4,r5
        ble ble1
        ble ble1
        fail
        fail
ble1:
ble1:
        mvi_h_gr r5,5
        mvi_h_gr r5,5
        cmp r4,r5
        cmp r4,r5
        ble ble2
        ble ble2
        fail
        fail
ble2:
ble2:
        mvi_h_gr r5,3
        mvi_h_gr r5,3
        cmp r4,r5
        cmp r4,r5
        ble ble3
        ble ble3
        b ble4
        b ble4
ble3:
ble3:
        fail
        fail
ble4:
ble4:
        pass
        pass
 
 

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