URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [arm/] [bic.cgs] - Diff between revs 24 and 33

Rev 24	Rev 33
`# arm testcase for bic`	`# arm testcase for bic`
`# mach: all`	`# mach: all`

`# ??? Unfinished, more tests needed.`	`# ??? Unfinished, more tests needed.`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`

`# bic$cond${set-cc?} $rd,$rn,$imm12`	`# bic$cond${set-cc?} $rd,$rn,$imm12`

`.global bic_imm`	`.global bic_imm`
`bic_imm:`	`bic_imm:`
`mvi_h_gr r4,1`	`mvi_h_gr r4,1`
`mvi_h_cnvz 0,0,0,0`	`mvi_h_cnvz 0,0,0,0`
`bic r5,r4,#0`	`bic r5,r4,#0`
`test_h_cnvz 0,0,0,0`	`test_h_cnvz 0,0,0,0`
`test_h_gr r5,1`	`test_h_gr r5,1`

`# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftimm}`	`# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftimm}`

`.global bic_reg_imm_shift`	`.global bic_reg_imm_shift`
`bic_reg_imm_shift:`	`bic_reg_imm_shift:`
`mvi_h_gr r4,7`	`mvi_h_gr r4,7`
`mvi_h_gr r5,1`	`mvi_h_gr r5,1`
`mvi_h_cnvz 0,0,0,0`	`mvi_h_cnvz 0,0,0,0`
`bic r6,r4,r5,lsl #1`	`bic r6,r4,r5,lsl #1`
`test_h_cnvz 0,0,0,0`	`test_h_cnvz 0,0,0,0`
`test_h_gr r6,5`	`test_h_gr r6,5`

`# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftreg}`	`# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftreg}`

`.global bic_reg_reg_shift`	`.global bic_reg_reg_shift`
`bic_reg_reg_shift:`	`bic_reg_reg_shift:`
`mvi_h_gr r4,7`	`mvi_h_gr r4,7`
`mvi_h_gr r5,1`	`mvi_h_gr r5,1`
`mvi_h_gr r6,1`	`mvi_h_gr r6,1`
`mvi_h_cnvz 0,0,0,0`	`mvi_h_cnvz 0,0,0,0`
`bic r7,r4,r5,lsl r6`	`bic r7,r4,r5,lsl r6`
`test_h_cnvz 0,0,0,0`	`test_h_cnvz 0,0,0,0`
`test_h_gr r7,5`	`test_h_gr r7,5`

`pass`	`pass`