URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [tmia.cgs] - Diff between revs 24 and 33

Rev 24	Rev 33
`# Intel(r) Wireless MMX(tm) technology testcase for TMIA`	`# Intel(r) Wireless MMX(tm) technology testcase for TMIA`
`# mach: xscale`	`# mach: xscale`
`# as: -mcpu=xscale+iwmmxt`	`# as: -mcpu=xscale+iwmmxt`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`

`.global tmia`	`.global tmia`
`tmia:`	`tmia:`
`# Enable access to CoProcessors 0 & 1 before`	`# Enable access to CoProcessors 0 & 1 before`
`# we attempt these instructions.`	`# we attempt these instructions.`

`mvi_h_gr r1, 3`	`mvi_h_gr r1, 3`
`mcr p15, 0, r1, cr15, cr1, 0`	`mcr p15, 0, r1, cr15, cr1, 0`

`# Test Multilply Accumulate`	`# Test Multilply Accumulate`

`mvi_h_gr r0, 0x11223344`	`mvi_h_gr r0, 0x11223344`
`mvi_h_gr r1, 0x55667788`	`mvi_h_gr r1, 0x55667788`
`mvi_h_gr r2, 0x12345678`	`mvi_h_gr r2, 0x12345678`
`mvi_h_gr r3, 0x9abcdef0`	`mvi_h_gr r3, 0x9abcdef0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`

`tmia wr0, r2, r3`	`tmia wr0, r2, r3`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`

`test_h_gr r0, 0x354f53c4`	`test_h_gr r0, 0x354f53c4`
`test_h_gr r1, 0x4e330b5e`	`test_h_gr r1, 0x4e330b5e`
`test_h_gr r2, 0x12345678`	`test_h_gr r2, 0x12345678`
`test_h_gr r3, 0x9abcdef0`	`test_h_gr r3, 0x9abcdef0`

`pass`	`pass`