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[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wavg2.cgs] - Diff between revs 24 and 33

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Rev 24 Rev 33
# Intel(r) Wireless MMX(tm) technology testcase for WAVG2
# Intel(r) Wireless MMX(tm) technology testcase for WAVG2
# mach: xscale
# mach: xscale
# as: -mcpu=xscale+iwmmxt
# as: -mcpu=xscale+iwmmxt
        .include "testutils.inc"
        .include "testutils.inc"
        start
        start
        .global wavg2
        .global wavg2
wavg2:
wavg2:
        # Enable access to CoProcessors 0 & 1 before
        # Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.
        # we attempt these instructions.
        mvi_h_gr   r1, 3
        mvi_h_gr   r1, 3
        mcr        p15, 0, r1, cr15, cr1, 0
        mcr        p15, 0, r1, cr15, cr1, 0
        # Test Byte Wide Averaging
        # Test Byte Wide Averaging
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x22222222
        mvi_h_gr   r3, 0x22222222
        mvi_h_gr   r4, 0
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
        mvi_h_gr   r5, 0
        tmcrr      wr0, r0, r1
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
        tmcrr      wr2, r4, r5
        wavg2b     wr2, wr0, wr1
        wavg2b     wr2, wr0, wr1
        tmrrc      r0, r1, wr0
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
        tmrrc      r4, r5, wr2
        test_h_gr  r0, 0x12345678
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x22222222
        test_h_gr  r3, 0x22222222
        test_h_gr  r4, 0x11223344
        test_h_gr  r4, 0x11223344
        test_h_gr  r5, 0x5e6f8089
        test_h_gr  r5, 0x5e6f8089
        # Test Byte Wide Averaging with Rounding
        # Test Byte Wide Averaging with Rounding
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x22222222
        mvi_h_gr   r3, 0x22222222
        mvi_h_gr   r4, 0
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
        mvi_h_gr   r5, 0
        tmcrr      wr0, r0, r1
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
        tmcrr      wr2, r4, r5
        wavg2br    wr2, wr0, wr1
        wavg2br    wr2, wr0, wr1
        tmrrc      r0, r1, wr0
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
        tmrrc      r4, r5, wr2
        test_h_gr  r0, 0x12345678
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x22222222
        test_h_gr  r3, 0x22222222
        test_h_gr  r4, 0x12233445
        test_h_gr  r4, 0x12233445
        test_h_gr  r5, 0x5e6f8089
        test_h_gr  r5, 0x5e6f8089
        # Test Half Word Wide Averaging
        # Test Half Word Wide Averaging
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x22222222
        mvi_h_gr   r3, 0x22222222
        mvi_h_gr   r4, 0
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
        mvi_h_gr   r5, 0
        tmcrr      wr0, r0, r1
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
        tmcrr      wr2, r4, r5
        wavg2h     wr2, wr0, wr1
        wavg2h     wr2, wr0, wr1
        tmrrc      r0, r1, wr0
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
        tmrrc      r4, r5, wr2
        test_h_gr  r0, 0x12345678
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x22222222
        test_h_gr  r3, 0x22222222
        test_h_gr  r4, 0x11a233c4
        test_h_gr  r4, 0x11a233c4
        test_h_gr  r5, 0x5e6f8089
        test_h_gr  r5, 0x5e6f8089
        # Test Half Word Wide Averaging with Rounding
        # Test Half Word Wide Averaging with Rounding
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r2, 0x11111111
        mvi_h_gr   r3, 0x22222222
        mvi_h_gr   r3, 0x22222222
        mvi_h_gr   r4, 0
        mvi_h_gr   r4, 0
        mvi_h_gr   r5, 0
        mvi_h_gr   r5, 0
        tmcrr      wr0, r0, r1
        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3
        tmcrr      wr1, r2, r3
        tmcrr      wr2, r4, r5
        tmcrr      wr2, r4, r5
        wavg2hr    wr2, wr0, wr1
        wavg2hr    wr2, wr0, wr1
        tmrrc      r0, r1, wr0
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        tmrrc      r2, r3, wr1
        tmrrc      r4, r5, wr2
        tmrrc      r4, r5, wr2
        test_h_gr  r0, 0x12345678
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0x11111111
        test_h_gr  r2, 0x11111111
        test_h_gr  r3, 0x22222222
        test_h_gr  r3, 0x22222222
        test_h_gr  r4, 0x11a333c5
        test_h_gr  r4, 0x11a333c5
        test_h_gr  r5, 0x5e6f8089
        test_h_gr  r5, 0x5e6f8089
        pass
        pass
 
 

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