URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wmin.cgs] - Diff between revs 24 and 33

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Rev 24	Rev 33
`# Intel(r) Wireless MMX(tm) technology testcase for WMIN`	`# Intel(r) Wireless MMX(tm) technology testcase for WMIN`
`# mach: xscale`	`# mach: xscale`
`# as: -mcpu=xscale+iwmmxt`	`# as: -mcpu=xscale+iwmmxt`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`

`.global wmin`	`.global wmin`
`wmin:`	`wmin:`
`# Enable access to CoProcessors 0 & 1 before`	`# Enable access to CoProcessors 0 & 1 before`
`# we attempt these instructions.`	`# we attempt these instructions.`

`mvi_h_gr r1, 3`	`mvi_h_gr r1, 3`
`mcr p15, 0, r1, cr15, cr1, 0`	`mcr p15, 0, r1, cr15, cr1, 0`

`# Test Unsigned Byte Minimum`	`# Test Unsigned Byte Minimum`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcde00`	`mvi_h_gr r1, 0x9abcde00`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x11111111`	`mvi_h_gr r3, 0x11111111`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wminub wr2, wr0, wr1`	`wminub wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcde00`	`test_h_gr r1, 0x9abcde00`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x11111111`	`test_h_gr r3, 0x11111111`
`test_h_gr r4, 0x11111111`	`test_h_gr r4, 0x11111111`
`test_h_gr r5, 0x11111100`	`test_h_gr r5, 0x11111100`

`# Test Signed Byte Minimum`	`# Test Signed Byte Minimum`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcde00`	`mvi_h_gr r1, 0x9abcde00`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x11111111`	`mvi_h_gr r3, 0x11111111`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wminsb wr2, wr0, wr1`	`wminsb wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcde00`	`test_h_gr r1, 0x9abcde00`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x11111111`	`test_h_gr r3, 0x11111111`
`test_h_gr r4, 0x11111111`	`test_h_gr r4, 0x11111111`
`test_h_gr r5, 0x9abcde00`	`test_h_gr r5, 0x9abcde00`

`# Test Unsigned Halfword Minimum`	`# Test Unsigned Halfword Minimum`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcde00`	`mvi_h_gr r1, 0x9abcde00`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x11111111`	`mvi_h_gr r3, 0x11111111`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wminuh wr2, wr0, wr1`	`wminuh wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcde00`	`test_h_gr r1, 0x9abcde00`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x11111111`	`test_h_gr r3, 0x11111111`
`test_h_gr r4, 0x11111111`	`test_h_gr r4, 0x11111111`
`test_h_gr r5, 0x11111111`	`test_h_gr r5, 0x11111111`

`# Test Signed Halfword Minimum`	`# Test Signed Halfword Minimum`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcde00`	`mvi_h_gr r1, 0x9abcde00`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x11111111`	`mvi_h_gr r3, 0x11111111`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wminsh wr2, wr0, wr1`	`wminsh wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcde00`	`test_h_gr r1, 0x9abcde00`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x11111111`	`test_h_gr r3, 0x11111111`
`test_h_gr r4, 0x11111111`	`test_h_gr r4, 0x11111111`
`test_h_gr r5, 0x9abcde00`	`test_h_gr r5, 0x9abcde00`

`# Test Unsigned Word Minimum`	`# Test Unsigned Word Minimum`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcde00`	`mvi_h_gr r1, 0x9abcde00`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x11111111`	`mvi_h_gr r3, 0x11111111`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wminuw wr2, wr0, wr1`	`wminuw wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcde00`	`test_h_gr r1, 0x9abcde00`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x11111111`	`test_h_gr r3, 0x11111111`
`test_h_gr r4, 0x11111111`	`test_h_gr r4, 0x11111111`
`test_h_gr r5, 0x11111111`	`test_h_gr r5, 0x11111111`

`# Test Signed Word Minimum`	`# Test Signed Word Minimum`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcde00`	`mvi_h_gr r1, 0x9abcde00`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x11111111`	`mvi_h_gr r3, 0x11111111`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wminsw wr2, wr0, wr1`	`wminsw wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcde00`	`test_h_gr r1, 0x9abcde00`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x11111111`	`test_h_gr r3, 0x11111111`
`test_h_gr r4, 0x11111111`	`test_h_gr r4, 0x11111111`
`test_h_gr r5, 0x9abcde00`	`test_h_gr r5, 0x9abcde00`

`pass`	`pass`

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Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wmin.cgs] - Diff between revs 24 and 33