URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wmul.cgs] - Diff between revs 24 and 33

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Rev 24	Rev 33
`# Intel(r) Wireless MMX(tm) technology testcase for WMUL`	`# Intel(r) Wireless MMX(tm) technology testcase for WMUL`
`# mach: xscale`	`# mach: xscale`
`# as: -mcpu=xscale+iwmmxt`	`# as: -mcpu=xscale+iwmmxt`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`

`.global wmul`	`.global wmul`
`wmul:`	`wmul:`
`# Enable access to CoProcessors 0 & 1 before`	`# Enable access to CoProcessors 0 & 1 before`
`# we attempt these instructions.`	`# we attempt these instructions.`

`mvi_h_gr r1, 3`	`mvi_h_gr r1, 3`
`mcr p15, 0, r1, cr15, cr1, 0`	`mcr p15, 0, r1, cr15, cr1, 0`

`# Test Unsigned, Most Significant Multiply`	`# Test Unsigned, Most Significant Multiply`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcdef0`	`mvi_h_gr r1, 0x9abcdef0`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x22222222`	`mvi_h_gr r3, 0x22222222`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wmulum wr2, wr0, wr1`	`wmulum wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcdef0`	`test_h_gr r1, 0x9abcdef0`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x22222222`	`test_h_gr r3, 0x22222222`
`test_h_gr r4, 0x013605c3`	`test_h_gr r4, 0x013605c3`
`test_h_gr r5, 0x14a11db9`	`test_h_gr r5, 0x14a11db9`

`# Test Unsigned, Least Significant Multiply`	`# Test Unsigned, Least Significant Multiply`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcdef0`	`mvi_h_gr r1, 0x9abcdef0`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x22222222`	`mvi_h_gr r3, 0x22222222`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wmulul wr2, wr0, wr1`	`wmulul wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcdef0`	`test_h_gr r1, 0x9abcdef0`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x22222222`	`test_h_gr r3, 0x22222222`
`test_h_gr r4, 0xa974b5f8`	`test_h_gr r4, 0xa974b5f8`
`test_h_gr r5, 0x84f87be0`	`test_h_gr r5, 0x84f87be0`

`# Test Signed, Most Significant Multiply`	`# Test Signed, Most Significant Multiply`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcdef0`	`mvi_h_gr r1, 0x9abcdef0`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x22222222`	`mvi_h_gr r3, 0x22222222`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wmulsm wr2, wr0, wr1`	`wmulsm wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcdef0`	`test_h_gr r1, 0x9abcdef0`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x22222222`	`test_h_gr r3, 0x22222222`
`test_h_gr r4, 0x013605c3`	`test_h_gr r4, 0x013605c3`
`test_h_gr r5, 0xf27ffb97`	`test_h_gr r5, 0xf27ffb97`

`# Test Signed, Least Significant Multiply`	`# Test Signed, Least Significant Multiply`

`mvi_h_gr r0, 0x12345678`	`mvi_h_gr r0, 0x12345678`
`mvi_h_gr r1, 0x9abcdef0`	`mvi_h_gr r1, 0x9abcdef0`
`mvi_h_gr r2, 0x11111111`	`mvi_h_gr r2, 0x11111111`
`mvi_h_gr r3, 0x22222222`	`mvi_h_gr r3, 0x22222222`
`mvi_h_gr r4, 0`	`mvi_h_gr r4, 0`
`mvi_h_gr r5, 0`	`mvi_h_gr r5, 0`

`tmcrr wr0, r0, r1`	`tmcrr wr0, r0, r1`
`tmcrr wr1, r2, r3`	`tmcrr wr1, r2, r3`
`tmcrr wr2, r4, r5`	`tmcrr wr2, r4, r5`

`wmulsl wr2, wr0, wr1`	`wmulsl wr2, wr0, wr1`

`tmrrc r0, r1, wr0`	`tmrrc r0, r1, wr0`
`tmrrc r2, r3, wr1`	`tmrrc r2, r3, wr1`
`tmrrc r4, r5, wr2`	`tmrrc r4, r5, wr2`

`test_h_gr r0, 0x12345678`	`test_h_gr r0, 0x12345678`
`test_h_gr r1, 0x9abcdef0`	`test_h_gr r1, 0x9abcdef0`
`test_h_gr r2, 0x11111111`	`test_h_gr r2, 0x11111111`
`test_h_gr r3, 0x22222222`	`test_h_gr r3, 0x22222222`
`test_h_gr r4, 0xa974b5f8`	`test_h_gr r4, 0xa974b5f8`
`test_h_gr r5, 0x84f87be0`	`test_h_gr r5, 0x84f87be0`

`pass`	`pass`

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wmul.cgs] - Diff between revs 24 and 33