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Rev 33 |
# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEL
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# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEL
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# mach: xscale
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# mach: xscale
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# as: -mcpu=xscale+iwmmxt
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# as: -mcpu=xscale+iwmmxt
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global wunpckel
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.global wunpckel
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wunpckel:
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wunpckel:
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# Enable access to CoProcessors 0 & 1 before
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# Enable access to CoProcessors 0 & 1 before
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# we attempt these instructions.
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# we attempt these instructions.
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mvi_h_gr r1, 3
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mvi_h_gr r1, 3
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mcr p15, 0, r1, cr15, cr1, 0
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mcr p15, 0, r1, cr15, cr1, 0
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# Test Unsigned Byte Unpacking
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# Test Unsigned Byte Unpacking
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mvi_h_gr r0, 0x12345687
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mvi_h_gr r0, 0x12345687
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0
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mvi_h_gr r2, 0
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mvi_h_gr r3, 0
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mvi_h_gr r3, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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wunpckelub wr1, wr0
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wunpckelub wr1, wr0
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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test_h_gr r0, 0x12345687
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test_h_gr r0, 0x12345687
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test_h_gr r1, 0x9abcdef0
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x00560087
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test_h_gr r2, 0x00560087
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test_h_gr r3, 0x00120034
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test_h_gr r3, 0x00120034
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# Test Signed Byte Unpacking
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# Test Signed Byte Unpacking
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mvi_h_gr r0, 0x12345687
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mvi_h_gr r0, 0x12345687
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0
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mvi_h_gr r2, 0
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mvi_h_gr r3, 0
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mvi_h_gr r3, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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wunpckelsb wr1, wr0
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wunpckelsb wr1, wr0
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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test_h_gr r0, 0x12345687
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test_h_gr r0, 0x12345687
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test_h_gr r1, 0x9abcdef0
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x0056ff87
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test_h_gr r2, 0x0056ff87
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test_h_gr r3, 0x00120034
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test_h_gr r3, 0x00120034
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# Test Unsigned Halfword Unpacking
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# Test Unsigned Halfword Unpacking
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0
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mvi_h_gr r2, 0
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mvi_h_gr r3, 0
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mvi_h_gr r3, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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wunpckeluh wr1, wr0
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wunpckeluh wr1, wr0
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x00005678
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test_h_gr r2, 0x00005678
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test_h_gr r3, 0x00001234
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test_h_gr r3, 0x00001234
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# Test Signed Halfword Unpacking
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# Test Signed Halfword Unpacking
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mvi_h_gr r0, 0x12348678
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mvi_h_gr r0, 0x12348678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0
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mvi_h_gr r2, 0
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mvi_h_gr r3, 0
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mvi_h_gr r3, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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wunpckelsh wr1, wr0
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wunpckelsh wr1, wr0
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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test_h_gr r0, 0x12348678
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test_h_gr r0, 0x12348678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0xffff8678
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test_h_gr r2, 0xffff8678
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test_h_gr r3, 0x00001234
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test_h_gr r3, 0x00001234
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# Test Unsigned Word Unpacking
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# Test Unsigned Word Unpacking
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r0, 0x12345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0
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mvi_h_gr r2, 0
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mvi_h_gr r3, 0
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mvi_h_gr r3, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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wunpckeluw wr1, wr0
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wunpckeluw wr1, wr0
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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test_h_gr r0, 0x12345678
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test_h_gr r0, 0x12345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x12345678
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test_h_gr r2, 0x12345678
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test_h_gr r3, 0x00000000
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test_h_gr r3, 0x00000000
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# Test Signed Word Unpacking
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# Test Signed Word Unpacking
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mvi_h_gr r0, 0x82345678
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mvi_h_gr r0, 0x82345678
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r1, 0x9abcdef0
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mvi_h_gr r2, 0
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mvi_h_gr r2, 0
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mvi_h_gr r3, 0
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mvi_h_gr r3, 0
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tmcrr wr0, r0, r1
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tmcrr wr0, r0, r1
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tmcrr wr1, r2, r3
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tmcrr wr1, r2, r3
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wunpckelsw wr1, wr0
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wunpckelsw wr1, wr0
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tmrrc r0, r1, wr0
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tmrrc r0, r1, wr0
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tmrrc r2, r3, wr1
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tmrrc r2, r3, wr1
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test_h_gr r0, 0x82345678
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test_h_gr r0, 0x82345678
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test_h_gr r1, 0x9abcdef0
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test_h_gr r1, 0x9abcdef0
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test_h_gr r2, 0x82345678
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test_h_gr r2, 0x82345678
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test_h_gr r3, 0xffffffff
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test_h_gr r3, 0xffffffff
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pass
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pass
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