OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [arm/] [misaligned1.ms] - Diff between revs 24 and 33

Only display areas with differences | Details | Blame | View Log

Rev 24 Rev 33
# Test LDR instructions with offsets misaligned by 1 byte.
# Test LDR instructions with offsets misaligned by 1 byte.
# mach(): all
# mach(): all
        .macro invalid
        .macro invalid
# This is "undefined" but it's not properly decoded yet.
# This is "undefined" but it's not properly decoded yet.
        .word 0x07ffffff
        .word 0x07ffffff
# This is stc which isn't recognized yet.
# This is stc which isn't recognized yet.
        stc 0,cr0,[r0]
        stc 0,cr0,[r0]
        .endm
        .endm
        .global _start
        .global _start
_start:
_start:
# Run some simple insns to confirm the engine is at least working.
# Run some simple insns to confirm the engine is at least working.
        nop
        nop
# Skip over output text.
# Skip over output text.
        bl do_test
        bl do_test
pass:
pass:
        .asciz "pass\n"
        .asciz "pass\n"
        .p2align 2
        .p2align 2
do_test:
do_test:
        mov r4, r14
        mov r4, r14
        bl continue
        bl continue
word1:
word1:
        .word 0x5555
        .word 0x5555
continue:
continue:
        ldr r6, [r14, #1]
        ldr r6, [r14, #1]
        ldr r7, word2
        ldr r7, word2
        cmp r6, r7
        cmp r6, r7
        # Failed.
        # Failed.
        bne done
        bne done
output_next:
output_next:
# Output a character (in arm mode).
# Output a character (in arm mode).
        mov r0,#3
        mov r0,#3
        mov r1,r4
        mov r1,r4
        swi #0x123456
        swi #0x123456
# Load next character, see if done.
# Load next character, see if done.
        add r4,r4,#1
        add r4,r4,#1
        sub r3,r3,r3
        sub r3,r3,r3
        ldrb r5,[r4,r3]
        ldrb r5,[r4,r3]
        teq r5,#0
        teq r5,#0
        bne output_next
        bne output_next
done:
done:
        mov r0,#0x18
        mov r0,#0x18
        ldr r1,exit_code
        ldr r1,exit_code
        swi #0x123456
        swi #0x123456
# If that fails, try to die with an invalid insn.
# If that fails, try to die with an invalid insn.
        invalid
        invalid
exit_code:
exit_code:
        .word 0x20026
        .word 0x20026
        .word 0xFFFFFFFF
        .word 0xFFFFFFFF
word2:
word2:
        .word 0x55000055
        .word 0x55000055
        .word 0xFFFFFFFF
        .word 0xFFFFFFFF
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.