URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [boundmv32.ms] - Diff between revs 24 and 33

Rev 24	Rev 33
`# mach: crisv32`	`# mach: crisv32`
`# xerror:`	`# xerror:`
`# output: program stopped with signal 4.\n`	`# output: program stopped with signal 4.\n`
`.include "testutils.inc"`	`.include "testutils.inc"`

`; Check that bound with a memory operand is invalid.`	`; Check that bound with a memory operand is invalid.`
`start`	`start`
`move.d 0f,r5`	`move.d 0f,r5`
`move.d r5,r3`	`move.d r5,r3`
`.byte 0xd5,0x39 ; bound.d [r5],r3 -- we can't assemble it.`	`.byte 0xd5,0x39 ; bound.d [r5],r3 -- we can't assemble it.`
`pass`	`pass`

`0:`	`0:`
`.dword 0b`	`.dword 0b`