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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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| Rev 24 |
Rev 33 |
# mach: crisv10
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# mach: crisv10
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# output: ff\nff\n0\n0\n80\n40\n20\n10\n8\n4\n2\n1\n80\n40\n20\n10\n8\n4\n2\n1\n42\n
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# output: ff\nff\n0\n0\n80\n40\n20\n10\n8\n4\n2\n1\n80\n40\n20\n10\n8\n4\n2\n1\n42\n
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; Check that flag settings affect ccr and dccr and vice versa.
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; Check that flag settings affect ccr and dccr and vice versa.
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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clear.d r3
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clear.d r3
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setf mbixnzvc
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setf mbixnzvc
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move ccr,r3
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move ccr,r3
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dumpr3
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dumpr3
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clear.d r3
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clear.d r3
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setf mbixnzvc
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setf mbixnzvc
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move dccr,r3
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move dccr,r3
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dumpr3
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dumpr3
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clear.d r3
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clear.d r3
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clearf mbixnzvc
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clearf mbixnzvc
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move ccr,r3
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move ccr,r3
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dumpr3
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dumpr3
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clear.d r3
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clear.d r3
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clearf mbixnzvc
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clearf mbixnzvc
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move dccr,r3
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move dccr,r3
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dumpr3
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dumpr3
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.macro testfr BIT REG
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.macro testfr BIT REG
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clear.d r3
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clear.d r3
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clearf mbixnzvc
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clearf mbixnzvc
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setf \BIT
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setf \BIT
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move \REG,r3
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move \REG,r3
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dumpr3
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dumpr3
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.endm
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.endm
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testfr m ccr
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testfr m ccr
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testfr b ccr
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testfr b ccr
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testfr i ccr
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testfr i ccr
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testfr x ccr
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testfr x ccr
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testfr n ccr
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testfr n ccr
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testfr z ccr
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testfr z ccr
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testfr v ccr
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testfr v ccr
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testfr c ccr
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testfr c ccr
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testfr m dccr
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testfr m dccr
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testfr b dccr
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testfr b dccr
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testfr i dccr
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testfr i dccr
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testfr x dccr
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testfr x dccr
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testfr n dccr
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testfr n dccr
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testfr z dccr
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testfr z dccr
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testfr v dccr
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testfr v dccr
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testfr c dccr
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testfr c dccr
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; Check only the nzvc bits; do the other bits in special tests as they're
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; Check only the nzvc bits; do the other bits in special tests as they're
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; implemented.
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; implemented.
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.macro test_get_cc N Z V C
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.macro test_get_cc N Z V C
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clearf znvc
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clearf znvc
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move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccr
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move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),ccr
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test_cc \N \Z \V \C
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test_cc \N \Z \V \C
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setf znvc
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setf znvc
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move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),dccr
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move ((\N << 3)|(\Z << 2)|(\V << 1)|\C),dccr
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test_cc \N \Z \V \C
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test_cc \N \Z \V \C
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move.d ((\N << 3)|(\Z << 2)|(\V << 1)|\C),r4
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move.d ((\N << 3)|(\Z << 2)|(\V << 1)|\C),r4
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setf znvc
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setf znvc
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move r4,ccr
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move r4,ccr
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test_cc \N \Z \V \C
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test_cc \N \Z \V \C
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clearf znvc
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clearf znvc
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move r4,dccr
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move r4,dccr
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test_cc \N \Z \V \C
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test_cc \N \Z \V \C
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.endm
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.endm
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test_get_cc 1 0 0 0
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test_get_cc 1 0 0 0
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test_get_cc 0 1 0 0
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test_get_cc 0 1 0 0
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test_get_cc 0 0 1 0
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test_get_cc 0 0 1 0
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test_get_cc 0 0 0 1
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test_get_cc 0 0 0 1
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move.d 0x42,r3
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move.d 0x42,r3
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dumpr3
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dumpr3
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quit
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quit
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