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[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [clrjmp1.ms] - Diff between revs 24 and 33

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Rev 24 Rev 33
# mach: crisv3 crisv8 crisv10 crisv32
# mach: crisv3 crisv8 crisv10 crisv32
# output: ffffff00\n
# output: ffffff00\n
; A bug resulting in a non-effectual clear.b discovered running the GCC
; A bug resulting in a non-effectual clear.b discovered running the GCC
; testsuite; jump actually wrote to p0.
; testsuite; jump actually wrote to p0.
 .include "testutils.inc"
 .include "testutils.inc"
 start
 start
 jump 1f
 jump 1f
 nop
 nop
 .p2align 8
 .p2align 8
1:
1:
 move.d y,r4
 move.d y,r4
 .if 0 == ..asm.arch.cris.v32
 .if 0 == ..asm.arch.cris.v32
; There was a bug causing this insn to set special register p0
; There was a bug causing this insn to set special register p0
; (byte-clear) to 8 (low 8 bits of location after insn).
; (byte-clear) to 8 (low 8 bits of location after insn).
 jump [r4+]
 jump [r4+]
 .endif
 .endif
1:
1:
 move.d 0f,r4
 move.d 0f,r4
; The corresponding bug would cause this insn too, to set p0.
; The corresponding bug would cause this insn too, to set p0.
 jump r4
 jump r4
 nop
 nop
 quit
 quit
0:
0:
 moveq -1,r3
 moveq -1,r3
 clear.b r3
 clear.b r3
 dumpr3
 dumpr3
 quit
 quit
y:
y:
 .dword 1b
 .dword 1b
 
 

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