URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 33 |
# mach: crisv32
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# mach: crisv32
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# ld: --section-start=.text=0
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# ld: --section-start=.text=0
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# sim: --cris-900000xx
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# sim: --cris-900000xx
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# xerror:
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# xerror:
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# output: b1e\n
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# output: b1e\n
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# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n
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# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n
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# output: program stopped with signal 11.\n
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# output: program stopped with signal 11.\n
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; Check that invalid access to the simulator area is recognized.
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; Check that invalid access to the simulator area is recognized.
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; "FAIL" area.
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; "FAIL" area.
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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move.d 0xb1e,$r3
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move.d 0xb1e,$r3
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dumpr3
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dumpr3
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move.d 0x90000008,$acr
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move.d 0x90000008,$acr
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clear.d [$acr]
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clear.d [$acr]
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move.d 0xbadc0de,$r3
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move.d 0xbadc0de,$r3
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dumpr3
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dumpr3
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0:
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0:
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ba 0b
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ba 0b
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nop
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nop
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