URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 24 |
Rev 33 |
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
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# mach: crisv0 crisv3 crisv8 crisv10 crisv32
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# output: aa117acd\n
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# output: aa117acd\n
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# output: eeaabb42\n
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# output: eeaabb42\n
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; Bug with move to special register in delay slot, due to
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; Bug with move to special register in delay slot, due to
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; special flush-insn-cache simulator use. Ordinary move worked;
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; special flush-insn-cache simulator use. Ordinary move worked;
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; special register caused branch to fail.
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; special register caused branch to fail.
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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move -1,srp
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move -1,srp
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move.d 0xaa117acd,r1
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move.d 0xaa117acd,r1
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moveq 3,r9
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moveq 3,r9
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cmpq 1,r9
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cmpq 1,r9
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bhi 0f
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bhi 0f
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move.d r1,r3
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move.d r1,r3
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fail
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fail
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0:
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0:
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dumpr3
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dumpr3
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move.d 0xeeaabb42,r1
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move.d 0xeeaabb42,r1
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moveq 3,r9
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moveq 3,r9
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cmpq 1,r9
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cmpq 1,r9
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bhi 0f
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bhi 0f
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move r1,srp
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move r1,srp
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fail
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fail
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0:
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0:
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move srp,r3
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move srp,r3
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dumpr3
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dumpr3
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quit
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quit
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