URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [movecpc.ms] - Diff between revs 24 and 33

Rev 24	Rev 33
`# mach: crisv3 crisv8 crisv10`	`# mach: crisv3 crisv8 crisv10`
`# xerror:`	`# xerror:`
`# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n`	`# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n`

`# We deliberately match both "read from" and "write to" above.`	`# We deliberately match both "read from" and "write to" above.`

`.include "testutils.inc"`	`.include "testutils.inc"`
`startnostack`	`startnostack`
`moveq -1,r3`	`moveq -1,r3`
`move.b 0x42,pc`	`move.b 0x42,pc`
`dumpr3`	`dumpr3`

`move.w 0x4321,pc`	`move.w 0x4321,pc`
`dumpr3`	`dumpr3`

`move.d 0x76543210,pc`	`move.d 0x76543210,pc`
`dumpr3`	`dumpr3`

`quit`	`quit`