URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 24 |
Rev 33 |
#mach: crisv10
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#mach: crisv10
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#output: Basic clock cycles, total @: 3\n
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#output: Basic clock cycles, total @: 3\n
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#output: Memory source stall cycles: 1\n
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#output: Memory source stall cycles: 1\n
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#output: Memory read-after-write stall cycles: 0\n
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#output: Memory read-after-write stall cycles: 0\n
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#output: Movem source stall cycles: 0\n
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#output: Movem source stall cycles: 0\n
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#output: Movem destination stall cycles: 0\n
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#output: Movem destination stall cycles: 0\n
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#output: Movem address stall cycles: 0\n
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#output: Movem address stall cycles: 0\n
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#output: Multiplication source stall cycles: 0\n
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#output: Multiplication source stall cycles: 0\n
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#output: Jump source stall cycles: 0\n
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#output: Jump source stall cycles: 0\n
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#output: Branch misprediction stall cycles: 0\n
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#output: Branch misprediction stall cycles: 0\n
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#output: Jump target stall cycles: 0\n
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#output: Jump target stall cycles: 0\n
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#sim: --cris-cycles=basic
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#sim: --cris-cycles=basic
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.include "testutils.inc"
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.include "testutils.inc"
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startnostack
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startnostack
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nop
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nop
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move.d 0xff004567,r5
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move.d 0xff004567,r5
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break 15
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break 15
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