URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [movepcd.ms] - Diff between revs 24 and 33

Rev 24	Rev 33
`# mach: crisv3 crisv8 crisv10`	`# mach: crisv3 crisv8 crisv10`
`# xerror:`	`# xerror:`
`# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n`	`# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n`

`# Both source and dest contain PC for "test.d r" (move.d r,r). Ideally,`	`# Both source and dest contain PC for "test.d r" (move.d r,r). Ideally,`
`# the output message should say "read" of PC, but we allow PC as source in`	`# the output message should say "read" of PC, but we allow PC as source in`
`# a move.d r,R insn, so there's no logical way to get that, short of a`	`# a move.d r,R insn, so there's no logical way to get that, short of a`
`# special pattern, which would be just too ugly. The output message says`	`# special pattern, which would be just too ugly. The output message says`
`# "write", but let's match "read" too so we won't fail if things suddenly`	`# "write", but let's match "read" too so we won't fail if things suddenly`
`# improve.`	`# improve.`

`.include "testutils.inc"`	`.include "testutils.inc"`
`startnostack`	`startnostack`
`setf`	`setf`
`test.d pc`	`test.d pc`
`quit`	`quit`