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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 33 |
# mach: crisv3 crisv8 crisv10 crisv32
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# mach: crisv3 crisv8 crisv10 crisv32
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# output: 5\nfffffff5\n5\nfffffff5\n0\n
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# output: 5\nfffffff5\n5\nfffffff5\n0\n
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; Movs between registers. Check that sign-extension is performed and the
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; Movs between registers. Check that sign-extension is performed and the
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; full register is set.
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; full register is set.
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.include "testutils.inc"
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.include "testutils.inc"
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.data
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.data
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x:
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x:
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.byte 5,-11
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.byte 5,-11
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.word 5,-11
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.word 5,-11
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.word 0
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.word 0
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start
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start
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move.d x,r5
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move.d x,r5
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moveq -1,r3
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moveq -1,r3
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movs.b [r5+],r3
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movs.b [r5+],r3
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test_move_cc 0 0 0 0
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test_move_cc 0 0 0 0
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dumpr3
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dumpr3
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moveq 0,r3
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moveq 0,r3
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movs.b [r5],r3
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movs.b [r5],r3
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test_move_cc 1 0 0 0
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test_move_cc 1 0 0 0
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addq 1,r5
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addq 1,r5
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dumpr3
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dumpr3
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moveq -1,r3
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moveq -1,r3
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movs.w [r5+],r3
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movs.w [r5+],r3
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test_move_cc 0 0 0 0
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test_move_cc 0 0 0 0
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dumpr3
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dumpr3
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moveq 0,r3
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moveq 0,r3
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movs.w [r5],r3
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movs.w [r5],r3
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test_move_cc 1 0 0 0
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test_move_cc 1 0 0 0
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addq 2,r5
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addq 2,r5
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dumpr3
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dumpr3
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movs.w [r5],r3
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movs.w [r5],r3
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test_move_cc 0 1 0 0
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test_move_cc 0 1 0 0
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dumpr3
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dumpr3
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quit
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quit
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