URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [msteppc1.ms] - Diff between revs 24 and 33

Rev 24	Rev 33
`# mach: crisv3 crisv8 crisv10`	`# mach: crisv3 crisv8 crisv10`
`# xerror:`	`# xerror:`
`# output: General register read of PC is not implemented.\n`	`# output: General register read of PC is not implemented.\n`
`# output: program stopped with signal 5.\n`	`# output: program stopped with signal 5.\n`

`.include "testutils.inc"`	`.include "testutils.inc"`
`start`	`start`
`mstep pc,r2`	`mstep pc,r2`