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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 33 |
; Checking read-after-write: write-MOF-then-read unaffected.
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; Checking read-after-write: write-MOF-then-read unaffected.
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#mach: crisv32
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#mach: crisv32
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#output: Basic clock cycles, total @: 4\n
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#output: Basic clock cycles, total @: 4\n
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#output: Memory source stall cycles: 0\n
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#output: Memory source stall cycles: 0\n
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#output: Memory read-after-write stall cycles: 0\n
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#output: Memory read-after-write stall cycles: 0\n
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#output: Movem source stall cycles: 0\n
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#output: Movem source stall cycles: 0\n
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#output: Movem destination stall cycles: 0\n
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#output: Movem destination stall cycles: 0\n
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#output: Movem address stall cycles: 0\n
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#output: Movem address stall cycles: 0\n
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#output: Multiplication source stall cycles: 0\n
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#output: Multiplication source stall cycles: 0\n
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#output: Jump source stall cycles: 0\n
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#output: Jump source stall cycles: 0\n
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#output: Branch misprediction stall cycles: 0\n
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#output: Branch misprediction stall cycles: 0\n
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#output: Jump target stall cycles: 0\n
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#output: Jump target stall cycles: 0\n
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#sim: --cris-cycles=basic
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#sim: --cris-cycles=basic
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.include "testutils.inc"
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.include "testutils.inc"
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startnostack
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startnostack
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.lcomm x,4
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.lcomm x,4
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.lcomm y,4
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.lcomm y,4
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move.d x,$r0
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move.d x,$r0
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move.d y,$r1
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move.d y,$r1
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move [$r0],$mof
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move [$r0],$mof
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move [$r1],$srp
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move [$r1],$srp
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break 15
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break 15
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