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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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| Rev 24 |
Rev 33 |
# mach: crisv32
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# mach: crisv32
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# output: 4000c3af\n40000020\n40000080\n40000000\n
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# output: 4000c3af\n40000020\n40000080\n40000000\n
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; Check that RFE affects CCS the right way.
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; Check that RFE affects CCS the right way.
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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; Set SPC to 1 to disable single step exceptions when S flag is set.
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; Set SPC to 1 to disable single step exceptions when S flag is set.
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move 1,spc
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move 1,spc
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; CCS:
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; CCS:
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; 31 24 23 16 15 8 7 0
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; 31 24 23 16 15 8 7 0
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; +---+-----------+-------+-------+-----------+---+---------------+
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; +---+-----------+-------+-------+-----------+---+---------------+
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; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C|
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; |Q M|S R P U I X N Z V C|S R P U I X N Z V C|S R P U I X N Z V C|
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; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| |
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; | |2 2 2 2 2 2 2 2 2 2|1 1 1 1 1 1 1 1 1 1| |
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; +---+-----------+-------+-------+-----------+---+---------------+
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; +---+-----------+-------+-------+-----------+---+---------------+
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; Clear S R P U I X N Z V C, set S1 R1 P1 (not U1) I1 X1 N1 Z1 V1 C1,
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; Clear S R P U I X N Z V C, set S1 R1 P1 (not U1) I1 X1 N1 Z1 V1 C1,
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; clear S2 R2 P2 U2 N2 Z2 V2 C2, Q; set I2 X2 M:
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; clear S2 R2 P2 U2 N2 Z2 V2 C2, Q; set I2 X2 M:
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; 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
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; 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
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move 0x430efc00,ccs
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move 0x430efc00,ccs
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test_cc 0 0 0 0
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test_cc 0 0 0 0
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rfe
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rfe
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test_cc 1 1 1 1
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test_cc 1 1 1 1
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move ccs,r3
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move ccs,r3
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dumpr3 ; 0x4000c3af
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dumpr3 ; 0x4000c3af
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rfe
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rfe
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test_cc 0 0 0 0
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test_cc 0 0 0 0
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move ccs,r3
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move ccs,r3
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dumpr3 ; 0x40000020
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dumpr3 ; 0x40000020
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rfe
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rfe
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test_cc 0 0 0 0
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test_cc 0 0 0 0
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move ccs,r3
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move ccs,r3
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dumpr3 ; 0x40000080
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dumpr3 ; 0x40000080
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or.w 0x100,r3
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or.w 0x100,r3
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move $r3,ccs
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move $r3,ccs
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rfe
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rfe
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move ccs,r3
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move ccs,r3
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dumpr3 ; 0x40000000
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dumpr3 ; 0x40000000
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quit
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quit
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