URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Only display areas with differences |
Details |
Blame |
View Log
Rev 24 |
Rev 33 |
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
|
# mach: crisv0 crisv3 crisv8 crisv10 crisv32
|
# output: 1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n0\n1\n1\n0\n1\n0\n0\n1\n1\n0\n1\n1\n0\n
|
# output: 1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n1\n0\n1\n0\n1\n0\n1\n0\n0\n1\n0\n1\n1\n0\n1\n0\n0\n1\n1\n0\n1\n1\n0\n
|
|
|
.include "testutils.inc"
|
.include "testutils.inc"
|
|
|
start
|
start
|
clearf nzvc
|
clearf nzvc
|
scc r3
|
scc r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
scs r3
|
scs r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
sne r3
|
sne r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
seq r3
|
seq r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
svc r3
|
svc r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
svs r3
|
svs r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
spl r3
|
spl r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
smi r3
|
smi r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
sls r3
|
sls r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
shi r3
|
shi r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
sge r3
|
sge r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
slt r3
|
slt r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
sgt r3
|
sgt r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
sle r3
|
sle r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
sa r3
|
sa r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
setf nzvc
|
setf nzvc
|
scc r3
|
scc r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
scs r3
|
scs r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
sne r3
|
sne r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
svc r3
|
svc r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
svs r3
|
svs r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
spl r3
|
spl r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
smi r3
|
smi r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
sls r3
|
sls r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
shi r3
|
shi r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
sge r3
|
sge r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
slt r3
|
slt r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
sgt r3
|
sgt r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
sle r3
|
sle r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
sa r3
|
sa r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
clearf n
|
clearf n
|
sge r3
|
sge r3
|
dumpr3 ; 0
|
dumpr3 ; 0
|
slt r3
|
slt r3
|
dumpr3 ; 1
|
dumpr3 ; 1
|
|
|
.if ..asm.arch.cris.v32
|
.if ..asm.arch.cris.v32
|
setf p
|
setf p
|
ssb r3
|
ssb r3
|
.else
|
.else
|
moveq 1,r3
|
moveq 1,r3
|
.endif
|
.endif
|
dumpr3 ; 1
|
dumpr3 ; 1
|
|
|
.if ..asm.arch.cris.v32
|
.if ..asm.arch.cris.v32
|
clearf p
|
clearf p
|
ssb r3
|
ssb r3
|
.else
|
.else
|
moveq 0,r3
|
moveq 0,r3
|
.endif
|
.endif
|
dumpr3 ; 0
|
dumpr3 ; 0
|
|
|
quit
|
quit
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.