URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [tmemv10.ms] - Diff between revs 24 and 33

Rev 24	Rev 33
`#mach: crisv10`	`#mach: crisv10`
`#output: Basic clock cycles, total @: 8\n`	`#output: Basic clock cycles, total @: 8\n`
`#output: Memory source stall cycles: 0\n`	`#output: Memory source stall cycles: 0\n`
`#output: Memory read-after-write stall cycles: 0\n`	`#output: Memory read-after-write stall cycles: 0\n`
`#output: Movem source stall cycles: 0\n`	`#output: Movem source stall cycles: 0\n`
`#output: Movem destination stall cycles: 0\n`	`#output: Movem destination stall cycles: 0\n`
`#output: Movem address stall cycles: 0\n`	`#output: Movem address stall cycles: 0\n`
`#output: Multiplication source stall cycles: 0\n`	`#output: Multiplication source stall cycles: 0\n`
`#output: Jump source stall cycles: 0\n`	`#output: Jump source stall cycles: 0\n`
`#output: Branch misprediction stall cycles: 0\n`	`#output: Branch misprediction stall cycles: 0\n`
`#output: Jump target stall cycles: 0\n`	`#output: Jump target stall cycles: 0\n`
`#sim: --cris-cycles=basic`	`#sim: --cris-cycles=basic`

`; Check that the memory indirection doesn't make the simulator barf.`	`; Check that the memory indirection doesn't make the simulator barf.`
`; Nothing deeper.`	`; Nothing deeper.`

`.include "testutils.inc"`	`.include "testutils.inc"`
`startnostack`	`startnostack`
`move.d 0f,r5`	`move.d 0f,r5`
`move.d [r5],r4`	`move.d [r5],r4`
`move.d [r5+],r3`	`move.d [r5+],r3`
`move.d [r5],r2`	`move.d [r5],r2`
`break 15`	`break 15`
`nop`	`nop`
`.p2align 2`	`.p2align 2`
`0:`	`0:`
`.dword 1,2,3`	`.dword 1,2,3`