OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [tmulv10.ms] - Diff between revs 24 and 33

Only display areas with differences | Details | Blame | View Log

Rev 24 Rev 33
#mach: crisv10
#mach: crisv10
#output: Basic clock cycles, total @: 9\n
#output: Basic clock cycles, total @: 9\n
#output: Memory source stall cycles: 0\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Memory read-after-write stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
#sim: --cris-cycles=basic
; Check that multiplications do not make the simulator barf.
; Check that multiplications do not make the simulator barf.
; Nothing deeper.
; Nothing deeper.
 .include "testutils.inc"
 .include "testutils.inc"
 startnostack
 startnostack
 moveq 1,r3
 moveq 1,r3
 moveq 2,r1
 moveq 2,r1
 moveq 1,r0
 moveq 1,r0
 muls.d r0,r1
 muls.d r0,r1
 muls.d r0,r3
 muls.d r0,r3
 mulu.d r1,r3
 mulu.d r1,r3
 break 15
 break 15
 nop
 nop
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.