#mach: crisv10
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#mach: crisv10
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#output: Basic clock cycles, total @: 45\n
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#output: Basic clock cycles, total @: 45\n
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#output: Memory source stall cycles: 0\n
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#output: Memory source stall cycles: 0\n
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#output: Memory read-after-write stall cycles: 0\n
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#output: Memory read-after-write stall cycles: 0\n
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#output: Movem source stall cycles: 0\n
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#output: Movem source stall cycles: 0\n
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#output: Movem destination stall cycles: 0\n
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#output: Movem destination stall cycles: 0\n
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#output: Movem address stall cycles: 0\n
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#output: Movem address stall cycles: 0\n
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#output: Multiplication source stall cycles: 0\n
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#output: Multiplication source stall cycles: 0\n
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#output: Jump source stall cycles: 0\n
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#output: Jump source stall cycles: 0\n
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#output: Branch misprediction stall cycles: 0\n
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#output: Branch misprediction stall cycles: 0\n
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#output: Jump target stall cycles: 0\n
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#output: Jump target stall cycles: 0\n
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#sim: --cris-cycles=basic
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#sim: --cris-cycles=basic
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; Check that movem to register basically looks ok cycle-wise.
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; Check that movem to register basically looks ok cycle-wise.
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; Nothing deep.
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; Nothing deep.
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.include "testutils.inc"
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.include "testutils.inc"
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startnostack
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startnostack
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move.d 0f,r5
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move.d 0f,r5
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moveq 0,r8
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moveq 0,r8
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moveq 0,r9
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moveq 0,r9
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; Adapted from crisv32 movem-to-memory penalty examples many
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; Adapted from crisv32 movem-to-memory penalty examples many
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; revisions ago.
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; revisions ago.
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movem [r5],r4
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movem [r5],r4
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test.d [r3] ; 3 cycle penalty on v32 (2 memory source, 1 movem dest).
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test.d [r3] ; 3 cycle penalty on v32 (2 memory source, 1 movem dest).
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movem [r5],r4
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movem [r5],r4
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subq 1,r8
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subq 1,r8
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test.d [r3] ; 2 cycle penalty on v32.
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test.d [r3] ; 2 cycle penalty on v32.
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movem [r5],r4
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movem [r5],r4
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subq 1,r1 ; 3 cycle penalty on v32.
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subq 1,r1 ; 3 cycle penalty on v32.
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movem [r5],r4
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movem [r5],r4
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add.d r8,r9
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add.d r8,r9
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subq 1,r1 ; 2 cycle penalty on v32.
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subq 1,r1 ; 2 cycle penalty on v32.
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movem [r5],r4
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movem [r5],r4
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add.d r8,r9
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add.d r8,r9
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subq 1, r9
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subq 1, r9
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subq 1, r1 ; 1 cycle penalty on v32.
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subq 1, r1 ; 1 cycle penalty on v32.
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break 15
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break 15
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.data
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.data
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.p2align 5
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.p2align 5
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0:
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0:
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.dword 0b
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.dword 0b
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.dword 0b
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.dword 0b
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.dword 0b
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.dword 0b
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.dword 0b
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.dword 0b
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.dword 0b
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.dword 0b
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