URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [cris/] [hw/] [rv-n-cris/] [trivial5.ms] - Diff between revs 24 and 33

Rev 24	Rev 33
`#mach: crisv10 crisv32`	`#mach: crisv10 crisv32`
`#sim(crisv10): --hw-device "/rv/trace? true"`	`#sim(crisv10): --hw-device "/rv/trace? true"`
`#sim(crisv32): --hw-device "/rv/trace? true"`	`#sim(crisv32): --hw-device "/rv/trace? true"`
`#output: /rv: WD\n`	`#output: /rv: WD\n`
`#output: /rv: REG R 0xd0000032\n`	`#output: /rv: REG R 0xd0000032\n`
`#output: /rv: := 0xabcdef01\n`	`#output: /rv: := 0xabcdef01\n`
`#output: /rv: REG W 0xd0000036 := 0xaabbccdd\n`	`#output: /rv: REG W 0xd0000036 := 0xaabbccdd\n`
`#output: /rv: REG R 0xd0000036\n`	`#output: /rv: REG R 0xd0000036\n`
`#output: /rv: := 0x76543210\n`	`#output: /rv: := 0x76543210\n`
`#output: pass\n`	`#output: pass\n`

`# Test trace output for read and write.`	`# Test trace output for read and write.`

`#r @,@srcdir@/trivial4.r`	`#r @,@srcdir@/trivial4.r`

`.include "trivial4.ms"`	`.include "trivial4.ms"`