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[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [fr30/] [add2.cgs] - Diff between revs 24 and 33

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Rev 24 Rev 33
# fr30 testcase for add2 $m4,$Ri
# fr30 testcase for add2 $m4,$Ri
# mach(): fr30
# mach(): fr30
        .include "testutils.inc"
        .include "testutils.inc"
        START
        START
        .text
        .text
        .global add
        .global add
add:
add:
        mvi_h_gr        30,r8
        mvi_h_gr        30,r8
        set_cc          0x0e    ; Set mask opposite of expected
        set_cc          0x0e    ; Set mask opposite of expected
        add2            -16,r8  ; Max value of immediate field
        add2            -16,r8  ; Max value of immediate field
        test_cc         0 0 0 1
        test_cc         0 0 0 1
        test_h_gr       14,r8
        test_h_gr       14,r8
        set_cc          0x0e    ; Set mask opposite of expected
        set_cc          0x0e    ; Set mask opposite of expected
        add2            -3,r8   ; Mid value of immediate field
        add2            -3,r8   ; Mid value of immediate field
        test_cc         0 0 0 1
        test_cc         0 0 0 1
        test_h_gr       11,r8
        test_h_gr       11,r8
        set_cc          0x0e    ; Set mask opposite of expected
        set_cc          0x0e    ; Set mask opposite of expected
        add2            -1,r8   ; Min value of immediate field
        add2            -1,r8   ; Min value of immediate field
        test_cc         0 0 0 1
        test_cc         0 0 0 1
        test_h_gr       10,r8
        test_h_gr       10,r8
        set_cc          0x0a    ; Set mask opposite of expected
        set_cc          0x0a    ; Set mask opposite of expected
        add2            -10,r8  ; Test zero and carry bits
        add2            -10,r8  ; Test zero and carry bits
        test_cc         0 1 0 1
        test_cc         0 1 0 1
        test_h_gr       0,r8
        test_h_gr       0,r8
        set_cc          0x07    ; Set mask opposite of expected
        set_cc          0x07    ; Set mask opposite of expected
        add2            -16,r8  ; Test negative bit
        add2            -16,r8  ; Test negative bit
        test_cc         1 0 0 0
        test_cc         1 0 0 0
        test_h_gr       -16,r8
        test_h_gr       -16,r8
        mvi_h_gr        0x80000000,r8
        mvi_h_gr        0x80000000,r8
        set_cc          0x0c    ; Set mask opposite of expected
        set_cc          0x0c    ; Set mask opposite of expected
        add2            -1,r8   ; Test overflow bit
        add2            -1,r8   ; Test overflow bit
        test_cc         0 0 1 1
        test_cc         0 0 1 1
        test_h_gr       0x7fffffff,r8
        test_h_gr       0x7fffffff,r8
        pass
        pass
 
 

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