URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [fr30/] [bandl.cgs] - Diff between revs 24 and 33

Rev 24	Rev 33
`# fr30 testcase for bandl $Rj,@$Ri`	`# fr30 testcase for bandl $Rj,@$Ri`
`# mach(): fr30`	`# mach(): fr30`

`.include "testutils.inc"`	`.include "testutils.inc"`

`START`	`START`

`.text`	`.text`
`.global bandl`	`.global bandl`
`bandl:`	`bandl:`
`; Test bandl $Rj,@$Ri`	`; Test bandl $Rj,@$Ri`
`mvi_h_mem 0x55555555,sp`	`mvi_h_mem 0x55555555,sp`
`set_cc 0x0f ; Condition codes should not change`	`set_cc 0x0f ; Condition codes should not change`
`bandl 0x0a,@sp`	`bandl 0x0a,@sp`
`test_cc 1 1 1 1`	`test_cc 1 1 1 1`
`test_h_mem 0x50555555,sp`	`test_h_mem 0x50555555,sp`

`mvi_h_mem 0xffffffff,sp`	`mvi_h_mem 0xffffffff,sp`
`set_cc 0x04 ; Condition codes should not change`	`set_cc 0x04 ; Condition codes should not change`
`bandl 0x0a,@sp`	`bandl 0x0a,@sp`
`test_cc 0 1 0 0`	`test_cc 0 1 0 0`
`test_h_mem 0xfaffffff,sp`	`test_h_mem 0xfaffffff,sp`

`mvi_h_mem 0x5effffff,sp`	`mvi_h_mem 0x5effffff,sp`
`set_cc 0x0a ; Condition codes should not change`	`set_cc 0x0a ; Condition codes should not change`
`bandl 0x07,@sp`	`bandl 0x07,@sp`
`test_cc 1 0 1 0`	`test_cc 1 0 1 0`
`test_h_mem 0x56ffffff,sp`	`test_h_mem 0x56ffffff,sp`

`pass`	`pass`