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| Rev 24 |
Rev 33 |
# fr30 testcase for div0s $Ri
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# fr30 testcase for div0s $Ri
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# mach(): fr30
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# mach(): fr30
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.include "testutils.inc"
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.include "testutils.inc"
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START
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START
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.text
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.text
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.global div0s
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.global div0s
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div0s:
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div0s:
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; Test div0s $Rj,$Ri
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; Test div0s $Rj,$Ri
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; example from the manual - negative dividend
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; example from the manual - negative dividend
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mvi_h_gr 0x0fffffff,r2
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mvi_h_gr 0x0fffffff,r2
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mvi_h_dr 0x00000000,mdh
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mvi_h_dr 0x00000000,mdh
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mvi_h_dr 0xfffffff0,mdl
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mvi_h_dr 0xfffffff0,mdl
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set_dbits 0x0 ; Set opposite of expected
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set_dbits 0x0 ; Set opposite of expected
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set_cc 0x0f ; Condition codes should not change
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set_cc 0x0f ; Condition codes should not change
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div0s r2
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div0s r2
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test_cc 1 1 1 1
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test_cc 1 1 1 1
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test_h_gr 0x0fffffff,r2
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test_h_gr 0x0fffffff,r2
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test_h_dr 0xffffffff,mdh
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test_h_dr 0xffffffff,mdh
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test_h_dr 0xfffffff0,mdl
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test_h_dr 0xfffffff0,mdl
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test_dbits 0x3
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test_dbits 0x3
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; negative divisor
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; negative divisor
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mvi_h_gr 0xffffffff,r2
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mvi_h_gr 0xffffffff,r2
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mvi_h_dr 0xffffffff,mdh
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mvi_h_dr 0xffffffff,mdh
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mvi_h_dr 0x7fffffff,mdl
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mvi_h_dr 0x7fffffff,mdl
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set_dbits 0x1 ; Set opposite of expected
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set_dbits 0x1 ; Set opposite of expected
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set_cc 0x0f ; Condition codes should not change
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set_cc 0x0f ; Condition codes should not change
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div0s r2
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div0s r2
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test_cc 1 1 1 1
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test_cc 1 1 1 1
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test_h_gr 0xffffffff,r2
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test_h_gr 0xffffffff,r2
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test_h_dr 0x00000000,mdh
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test_h_dr 0x00000000,mdh
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test_h_dr 0x7fffffff,mdl
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test_h_dr 0x7fffffff,mdl
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test_dbits 0x2
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test_dbits 0x2
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; Both sign bits 0
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; Both sign bits 0
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mvi_h_gr 0x0fffffff,r2
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mvi_h_gr 0x0fffffff,r2
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mvi_h_dr 0xffffffff,mdh
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mvi_h_dr 0xffffffff,mdh
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mvi_h_dr 0x7ffffff0,mdl
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mvi_h_dr 0x7ffffff0,mdl
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set_dbits 0x3 ; Set opposite of expected
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set_dbits 0x3 ; Set opposite of expected
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set_cc 0x0f ; Condition codes should not change
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set_cc 0x0f ; Condition codes should not change
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div0s r2
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div0s r2
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test_cc 1 1 1 1
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test_cc 1 1 1 1
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test_h_gr 0x0fffffff,r2
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test_h_gr 0x0fffffff,r2
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test_h_dr 0x00000000,mdh
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test_h_dr 0x00000000,mdh
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test_h_dr 0x7ffffff0,mdl
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test_h_dr 0x7ffffff0,mdl
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test_dbits 0x0
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test_dbits 0x0
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; Both sign bits 1
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; Both sign bits 1
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mvi_h_gr 0xffffffff,r2
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mvi_h_gr 0xffffffff,r2
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mvi_h_dr 0x00000000,mdh
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mvi_h_dr 0x00000000,mdh
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mvi_h_dr 0xffffffff,mdl
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mvi_h_dr 0xffffffff,mdl
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set_dbits 0x2 ; Set opposite of expected
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set_dbits 0x2 ; Set opposite of expected
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set_cc 0x0f ; Condition codes should not change
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set_cc 0x0f ; Condition codes should not change
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div0s r2
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div0s r2
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test_cc 1 1 1 1
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test_cc 1 1 1 1
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test_h_gr 0xffffffff,r2
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test_h_gr 0xffffffff,r2
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test_h_dr 0xffffffff,mdh
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test_h_dr 0xffffffff,mdh
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test_h_dr 0xffffffff,mdl
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test_h_dr 0xffffffff,mdl
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test_dbits 0x1
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test_dbits 0x1
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pass
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pass
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