OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [fr30/] [extuh.cgs] - Diff between revs 24 and 33

Only display areas with differences | Details | Blame | View Log

Rev 24 Rev 33
# fr30 testcase for extuh $Ri
# fr30 testcase for extuh $Ri
# mach(): fr30
# mach(): fr30
        .include "testutils.inc"
        .include "testutils.inc"
        START
        START
        .text
        .text
        .global extuh
        .global extuh
extuh:
extuh:
        ; Test extuh $Ri
        ; Test extuh $Ri
        mvi_h_gr        0,r7
        mvi_h_gr        0,r7
        set_cc          0x0f            ; Condition codes are irrelevent
        set_cc          0x0f            ; Condition codes are irrelevent
        extuh           r7
        extuh           r7
        test_cc         1 1 1 1
        test_cc         1 1 1 1
        test_h_gr       0,r7
        test_h_gr       0,r7
        mvi_h_gr        0x7f,r7
        mvi_h_gr        0x7f,r7
        set_cc          0x0e            ; Condition codes are irrelevent
        set_cc          0x0e            ; Condition codes are irrelevent
        extuh           r7
        extuh           r7
        test_cc         1 1 1 0
        test_cc         1 1 1 0
        test_h_gr       0x7f,r7
        test_h_gr       0x7f,r7
        mvi_h_gr        0x80,r7
        mvi_h_gr        0x80,r7
        set_cc          0x0d            ; Condition codes are irrelevent
        set_cc          0x0d            ; Condition codes are irrelevent
        extuh           r7
        extuh           r7
        test_cc         1 1 0 1
        test_cc         1 1 0 1
        test_h_gr       0x80,r7
        test_h_gr       0x80,r7
        mvi_h_gr        0x7fff,r7
        mvi_h_gr        0x7fff,r7
        set_cc          0x0e            ; Condition codes are irrelevent
        set_cc          0x0e            ; Condition codes are irrelevent
        extuh           r7
        extuh           r7
        test_cc         1 1 1 0
        test_cc         1 1 1 0
        test_h_gr       0x7fff,r7
        test_h_gr       0x7fff,r7
        mvi_h_gr        0x8000,r7
        mvi_h_gr        0x8000,r7
        set_cc          0x0d            ; Condition codes are irrelevent
        set_cc          0x0d            ; Condition codes are irrelevent
        extuh           r7
        extuh           r7
        test_cc         1 1 0 1
        test_cc         1 1 0 1
        test_h_gr       0x8000,r7
        test_h_gr       0x8000,r7
        mvi_h_gr        0xffff7fff,r7
        mvi_h_gr        0xffff7fff,r7
        set_cc          0x0c            ; Condition codes are irrelevent
        set_cc          0x0c            ; Condition codes are irrelevent
        extuh           r7
        extuh           r7
        test_cc         1 1 0 0
        test_cc         1 1 0 0
        test_h_gr       0x7fff,r7
        test_h_gr       0x7fff,r7
        mvi_h_gr        0xffff8000,r7
        mvi_h_gr        0xffff8000,r7
        set_cc          0x0b            ; Condition codes are irrelevent
        set_cc          0x0b            ; Condition codes are irrelevent
        extuh           r7
        extuh           r7
        test_cc         1 0 1 1
        test_cc         1 0 1 1
        test_h_gr       0x8000,r7
        test_h_gr       0x8000,r7
        pass
        pass
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.