URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [fr30/] [int.cgs] - Diff between revs 24 and 33

Rev 24	Rev 33
`# fr30 testcase for int $u8`	`# fr30 testcase for int $u8`
`# mach(): fr30`	`# mach(): fr30`

`.include "testutils.inc"`	`.include "testutils.inc"`

`START`	`START`

`.text`	`.text`
`.global int`	`.global int`
`int:`	`int:`
`; Test int $u8 - setup and test an interrupt #0xfd (randomly chosen)`	`; Test int $u8 - setup and test an interrupt #0xfd (randomly chosen)`
`mvr_h_gr tbr,r7`	`mvr_h_gr tbr,r7`
`inci_h_gr 8,r7`	`inci_h_gr 8,r7`
`mvi_h_mem pass,r7`	`mvi_h_mem pass,r7`
`mvi_h_gr doint,r9`	`mvi_h_gr doint,r9`
`inci_h_gr 2,r9`	`inci_h_gr 2,r9`
`mvr_h_gr ssp,r10`	`mvr_h_gr ssp,r10`
`set_cc 0x0f ; Condition codes should not change`	`set_cc 0x0f ; Condition codes should not change`
`set_s_user ; Set opposite of expected`	`set_s_user ; Set opposite of expected`
`set_i 1 ; Set opposite of expected`	`set_i 1 ; Set opposite of expected`
`mvr_h_gr ps,r8`	`mvr_h_gr ps,r8`
`doint: int 0xfd`	`doint: int 0xfd`
`fail`	`fail`

`pass:`	`pass:`
`test_cc 1 1 1 1`	`test_cc 1 1 1 1`
`test_s_system`	`test_s_system`
`test_i 0`	`test_i 0`
`inci_h_gr -4,r10`	`inci_h_gr -4,r10`
`testr_h_mem r8,r10`	`testr_h_mem r8,r10`
`inci_h_gr -4,r10`	`inci_h_gr -4,r10`
`testr_h_mem r9,r10`	`testr_h_mem r9,r10`
`testr_h_dr r10,ssp`	`testr_h_dr r10,ssp`

`pass`	`pass`