# fr30 testcase for lsl $Rj,$Ri, lsl $u4,$Rj
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# fr30 testcase for lsl $Rj,$Ri, lsl $u4,$Rj
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# mach(): fr30
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# mach(): fr30
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.include "testutils.inc"
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.include "testutils.inc"
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START
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START
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.text
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.text
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.global lsl
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.global lsl
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lsl:
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lsl:
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; Test lsl $Rj,$Ri
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; Test lsl $Rj,$Ri
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mvi_h_gr 0xdeadbee0,r7 ; Shift by 0
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mvi_h_gr 0xdeadbee0,r7 ; Shift by 0
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mvi_h_gr 2,r8
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mvi_h_gr 2,r8
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set_cc 0x0d ; Set mask opposite of expected
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set_cc 0x0d ; Set mask opposite of expected
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lsl r7,r8
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lsl r7,r8
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test_cc 0 0 0 0
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test_cc 0 0 0 0
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test_h_gr 2,r8
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test_h_gr 2,r8
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mvi_h_gr 0xdeadbee1,r7 ; Shift by 1
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mvi_h_gr 0xdeadbee1,r7 ; Shift by 1
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mvi_h_gr 2,r8
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mvi_h_gr 2,r8
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set_cc 0x0f ; Set mask opposite of expected
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set_cc 0x0f ; Set mask opposite of expected
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lsl r7,r8
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lsl r7,r8
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test_cc 0 0 1 0
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test_cc 0 0 1 0
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test_h_gr 4,r8
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test_h_gr 4,r8
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mvi_h_gr 0xdeadbeff,r7 ; Shift by 31
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mvi_h_gr 0xdeadbeff,r7 ; Shift by 31
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mvi_h_gr 1,r8
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mvi_h_gr 1,r8
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set_cc 0x07 ; Set mask opposite of expected
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set_cc 0x07 ; Set mask opposite of expected
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lsl r7,r8
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lsl r7,r8
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test_cc 1 0 1 0
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test_cc 1 0 1 0
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test_h_gr 0x80000000,r8
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test_h_gr 0x80000000,r8
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mvi_h_gr 0xdeadbeff,r7 ; clear register
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mvi_h_gr 0xdeadbeff,r7 ; clear register
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mvi_h_gr 2,r8
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mvi_h_gr 2,r8
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set_cc 0x0a ; Set mask opposite of expected
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set_cc 0x0a ; Set mask opposite of expected
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lsl r7,r8
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lsl r7,r8
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test_cc 0 1 1 1
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test_cc 0 1 1 1
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test_h_gr 0x00000000,r8
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test_h_gr 0x00000000,r8
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; Test lsl $u4Ri
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; Test lsl $u4Ri
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mvi_h_gr 2,r8
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mvi_h_gr 2,r8
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set_cc 0x0d ; Set mask opposite of expected
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set_cc 0x0d ; Set mask opposite of expected
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lsl 0,r8
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lsl 0,r8
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test_cc 0 0 0 0
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test_cc 0 0 0 0
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test_h_gr 2,r8
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test_h_gr 2,r8
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mvi_h_gr 2,r8
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mvi_h_gr 2,r8
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set_cc 0x0f ; Set mask opposite of expected
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set_cc 0x0f ; Set mask opposite of expected
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lsl 1,r8
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lsl 1,r8
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test_cc 0 0 1 0
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test_cc 0 0 1 0
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test_h_gr 4,r8
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test_h_gr 4,r8
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mvi_h_gr 1,r8
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mvi_h_gr 1,r8
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set_cc 0x0e ; Set mask opposite of expected
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set_cc 0x0e ; Set mask opposite of expected
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lsl 15,r8
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lsl 15,r8
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test_cc 0 0 1 0
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test_cc 0 0 1 0
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test_h_gr 0x00008000,r8
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test_h_gr 0x00008000,r8
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mvi_h_gr 0x00020000,r8
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mvi_h_gr 0x00020000,r8
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set_cc 0x0a ; Set mask opposite of expected
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set_cc 0x0a ; Set mask opposite of expected
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lsl 15,r8
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lsl 15,r8
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test_cc 0 1 1 1
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test_cc 0 1 1 1
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test_h_gr 0x00000000,r8
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test_h_gr 0x00000000,r8
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pass
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pass
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