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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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| Rev 24 |
Rev 33 |
# frv testcase for bcnolr
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# frv testcase for bcnolr
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# mach: all
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# mach: all
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global bcnolr
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.global bcnolr
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bcnolr:
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bcnolr:
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; ccond is true
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; ccond is true
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set_spr_immed 128,lcr
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set_spr_immed 128,lcr
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_icc 0x0 0
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set_icc 0x0 0
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bcnolr
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bcnolr
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set_icc 0x1 1
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set_icc 0x1 1
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bcnolr
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bcnolr
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set_icc 0x2 2
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set_icc 0x2 2
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bcnolr
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bcnolr
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set_icc 0x3 3
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set_icc 0x3 3
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bcnolr
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bcnolr
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set_icc 0x4 0
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set_icc 0x4 0
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bcnolr
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bcnolr
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set_icc 0x5 1
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set_icc 0x5 1
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bcnolr
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bcnolr
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set_icc 0x6 2
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set_icc 0x6 2
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bcnolr
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bcnolr
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set_icc 0x7 3
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set_icc 0x7 3
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bcnolr
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bcnolr
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set_icc 0x8 0
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set_icc 0x8 0
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bcnolr
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bcnolr
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set_icc 0x9 1
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set_icc 0x9 1
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bcnolr
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bcnolr
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set_icc 0xa 2
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set_icc 0xa 2
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bcnolr
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bcnolr
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set_icc 0xb 3
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set_icc 0xb 3
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bcnolr
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bcnolr
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set_icc 0xc 0
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set_icc 0xc 0
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bcnolr
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bcnolr
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set_icc 0xd 1
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set_icc 0xd 1
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bcnolr
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bcnolr
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set_icc 0xe 2
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set_icc 0xe 2
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bcnolr
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bcnolr
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set_icc 0xf 3
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set_icc 0xf 3
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bcnolr
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bcnolr
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; ccond is true
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; ccond is true
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_icc 0x0 0
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set_icc 0x0 0
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x1 1
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set_icc 0x1 1
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x2 2
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set_icc 0x2 2
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x3 3
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set_icc 0x3 3
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x4 0
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set_icc 0x4 0
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x5 1
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set_icc 0x5 1
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x6 2
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set_icc 0x6 2
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x7 3
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set_icc 0x7 3
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x8 0
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set_icc 0x8 0
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x9 1
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set_icc 0x9 1
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0xa 2
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set_icc 0xa 2
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0xb 3
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set_icc 0xb 3
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0xc 0
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set_icc 0xc 0
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0xd 1
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set_icc 0xd 1
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0xe 2
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set_icc 0xe 2
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0xf 3
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set_icc 0xf 3
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bcnolr
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bcnolr
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; ccond is false
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; ccond is false
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set_spr_immed 128,lcr
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set_spr_immed 128,lcr
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_icc 0x0 0
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set_icc 0x0 0
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bcnolr
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bcnolr
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set_icc 0x1 1
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set_icc 0x1 1
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bcnolr
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bcnolr
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set_icc 0x2 2
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set_icc 0x2 2
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bcnolr
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bcnolr
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set_icc 0x3 3
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set_icc 0x3 3
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bcnolr
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bcnolr
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set_icc 0x4 0
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set_icc 0x4 0
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bcnolr
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bcnolr
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set_icc 0x5 1
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set_icc 0x5 1
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bcnolr
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bcnolr
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set_icc 0x6 2
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set_icc 0x6 2
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bcnolr
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bcnolr
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set_icc 0x7 3
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set_icc 0x7 3
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bcnolr
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bcnolr
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set_icc 0x8 0
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set_icc 0x8 0
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bcnolr
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bcnolr
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set_icc 0x9 1
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set_icc 0x9 1
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bcnolr
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bcnolr
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set_icc 0xa 2
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set_icc 0xa 2
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bcnolr
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bcnolr
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set_icc 0xb 3
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set_icc 0xb 3
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bcnolr
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bcnolr
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set_icc 0xc 0
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set_icc 0xc 0
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bcnolr
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bcnolr
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set_icc 0xd 1
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set_icc 0xd 1
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bcnolr
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bcnolr
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set_icc 0xe 2
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set_icc 0xe 2
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bcnolr
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bcnolr
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set_icc 0xf 3
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set_icc 0xf 3
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bcnolr
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bcnolr
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; ccond is false
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; ccond is false
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_icc 0x0 0
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set_icc 0x0 0
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x1 1
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set_icc 0x1 1
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x2 2
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set_icc 0x2 2
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x3 3
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set_icc 0x3 3
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x4 0
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set_icc 0x4 0
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x5 1
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set_icc 0x5 1
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x6 2
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set_icc 0x6 2
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x7 3
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set_icc 0x7 3
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x8 0
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set_icc 0x8 0
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0x9 1
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set_icc 0x9 1
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0xa 2
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set_icc 0xa 2
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0xb 3
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set_icc 0xb 3
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0xc 0
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set_icc 0xc 0
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0xd 1
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set_icc 0xd 1
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0xe 2
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set_icc 0xe 2
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bcnolr
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bcnolr
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_icc 0xf 3
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set_icc 0xf 3
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bcnolr
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bcnolr
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pass
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pass
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bad:
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bad:
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fail
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fail
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