URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [frv/] [bhilr.cgs] - Diff between revs 24 and 33

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Rev 24	Rev 33
`# frv testcase for bhilr $ICCi,$hint`	`# frv testcase for bhilr $ICCi,$hint`
`# mach: all`	`# mach: all`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`

`.global bhilr`	`.global bhilr`
`bhilr:`	`bhilr:`
`set_spr_addr ok1,lr`	`set_spr_addr ok1,lr`
`set_icc 0x0 0`	`set_icc 0x0 0`
`bhilr icc0,0`	`bhilr icc0,0`
`fail`	`fail`
`ok1:`	`ok1:`
`set_spr_addr bad,lr`	`set_spr_addr bad,lr`
`set_icc 0x1 1`	`set_icc 0x1 1`
`bhilr icc1,1`	`bhilr icc1,1`

`set_spr_addr ok3,lr`	`set_spr_addr ok3,lr`
`set_icc 0x2 2`	`set_icc 0x2 2`
`bhilr icc2,2`	`bhilr icc2,2`
`fail`	`fail`
`ok3:`	`ok3:`
`set_spr_addr bad,lr`	`set_spr_addr bad,lr`
`set_icc 0x3 3`	`set_icc 0x3 3`
`bhilr icc3,3`	`bhilr icc3,3`

`set_spr_addr bad,lr`	`set_spr_addr bad,lr`
`set_icc 0x4 0`	`set_icc 0x4 0`
`bhilr icc0,0`	`bhilr icc0,0`

`set_spr_addr bad,lr`	`set_spr_addr bad,lr`
`set_icc 0x5 1`	`set_icc 0x5 1`
`bhilr icc1,1`	`bhilr icc1,1`

`set_spr_addr bad,lr`	`set_spr_addr bad,lr`
`set_icc 0x6 2`	`set_icc 0x6 2`
`bhilr icc2,2`	`bhilr icc2,2`

`set_spr_addr bad,lr`	`set_spr_addr bad,lr`
`set_icc 0x7 3`	`set_icc 0x7 3`
`bhilr icc3,3`	`bhilr icc3,3`

`set_spr_addr ok9,lr`	`set_spr_addr ok9,lr`
`set_icc 0x8 0`	`set_icc 0x8 0`
`bhilr icc0,0`	`bhilr icc0,0`
`fail`	`fail`
`ok9:`	`ok9:`
`set_spr_addr bad,lr`	`set_spr_addr bad,lr`
`set_icc 0x9 1`	`set_icc 0x9 1`
`bhilr icc1,1`	`bhilr icc1,1`

`set_spr_addr okb,lr`	`set_spr_addr okb,lr`
`set_icc 0xa 2`	`set_icc 0xa 2`
`bhilr icc2,2`	`bhilr icc2,2`
`fail`	`fail`
`okb:`	`okb:`
`set_spr_addr bad,lr`	`set_spr_addr bad,lr`
`set_icc 0xb 3`	`set_icc 0xb 3`
`bhilr icc3,3`	`bhilr icc3,3`

`set_spr_addr bad,lr`	`set_spr_addr bad,lr`
`set_icc 0xc 0`	`set_icc 0xc 0`
`bhilr icc0,0`	`bhilr icc0,0`

`set_spr_addr bad,lr`	`set_spr_addr bad,lr`
`set_icc 0xd 1`	`set_icc 0xd 1`
`bhilr icc1,1`	`bhilr icc1,1`

`set_spr_addr bad,lr`	`set_spr_addr bad,lr`
`set_icc 0xe 2`	`set_icc 0xe 2`
`bhilr icc2,2`	`bhilr icc2,2`

`set_spr_addr bad,lr`	`set_spr_addr bad,lr`
`set_icc 0xf 3`	`set_icc 0xf 3`
`bhilr icc3,3`	`bhilr icc3,3`

`pass`	`pass`
`bad:`	`bad:`
`fail`	`fail`

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [frv/] [bhilr.cgs] - Diff between revs 24 and 33