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[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [frv/] [cldsb.cgs] - Diff between revs 24 and 33

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Rev 24 Rev 33
# frv testcase for cldsb @($GRi,$GRj),$GRk,$CCi,$cond
# frv testcase for cldsb @($GRi,$GRj),$GRk,$CCi,$cond
# mach: all
# mach: all
        .include "testutils.inc"
        .include "testutils.inc"
        start
        start
        .global cldsb
        .global cldsb
cldsb:
cldsb:
        set_spr_immed   0x1b1b,cccr
        set_spr_immed   0x1b1b,cccr
        set_mem_limmed  0xdead,0xbeef,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_gr_limmed   0xbeef,0xdead,gr8
        set_gr_limmed   0xbeef,0xdead,gr8
        set_gr_immed    0,gr7
        set_gr_immed    0,gr7
        cldsb           @(sp,gr7),gr8,cc0,1
        cldsb           @(sp,gr7),gr8,cc0,1
        test_gr_limmed  0xffff,0xffde,gr8
        test_gr_limmed  0xffff,0xffde,gr8
        set_gr_immed    1,gr7
        set_gr_immed    1,gr7
        cldsb           @(sp,gr7),gr8,cc0,1
        cldsb           @(sp,gr7),gr8,cc0,1
        test_gr_limmed  0xffff,0xffad,gr8
        test_gr_limmed  0xffff,0xffad,gr8
        set_mem_limmed  0xffff,0xff00,sp
        set_mem_limmed  0xffff,0xff00,sp
        inc_gr_immed    4,sp
        inc_gr_immed    4,sp
        set_gr_immed    -1,gr7
        set_gr_immed    -1,gr7
        cldsb           @(sp,gr7),gr8,cc4,1
        cldsb           @(sp,gr7),gr8,cc4,1
        test_gr_immed   0,gr8
        test_gr_immed   0,gr8
        set_mem_limmed  0xdead,0xbeef,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_gr_limmed   0xbeef,0xdead,gr8
        set_gr_limmed   0xbeef,0xdead,gr8
        set_gr_immed    0,gr7
        set_gr_immed    0,gr7
        cldsb           @(sp,gr7),gr8,cc0,0
        cldsb           @(sp,gr7),gr8,cc0,0
        test_gr_limmed  0xbeef,0xdead,gr8
        test_gr_limmed  0xbeef,0xdead,gr8
        set_gr_immed    1,gr7
        set_gr_immed    1,gr7
        cldsb           @(sp,gr7),gr8,cc0,0
        cldsb           @(sp,gr7),gr8,cc0,0
        test_gr_limmed  0xbeef,0xdead,gr8
        test_gr_limmed  0xbeef,0xdead,gr8
        set_mem_limmed  0xffff,0xff00,sp
        set_mem_limmed  0xffff,0xff00,sp
        inc_gr_immed    4,sp
        inc_gr_immed    4,sp
        set_gr_immed    -1,gr7
        set_gr_immed    -1,gr7
        cldsb           @(sp,gr7),gr8,cc4,0
        cldsb           @(sp,gr7),gr8,cc4,0
        test_gr_limmed  0xbeef,0xdead,gr8
        test_gr_limmed  0xbeef,0xdead,gr8
        set_mem_limmed  0xdead,0xbeef,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_gr_limmed   0xbeef,0xdead,gr8
        set_gr_limmed   0xbeef,0xdead,gr8
        set_gr_immed    0,gr7
        set_gr_immed    0,gr7
        cldsb           @(sp,gr7),gr8,cc1,0
        cldsb           @(sp,gr7),gr8,cc1,0
        test_gr_limmed  0xffff,0xffde,gr8
        test_gr_limmed  0xffff,0xffde,gr8
        set_gr_immed    1,gr7
        set_gr_immed    1,gr7
        cldsb           @(sp,gr7),gr8,cc1,0
        cldsb           @(sp,gr7),gr8,cc1,0
        test_gr_limmed  0xffff,0xffad,gr8
        test_gr_limmed  0xffff,0xffad,gr8
        set_mem_limmed  0xffff,0xff00,sp
        set_mem_limmed  0xffff,0xff00,sp
        inc_gr_immed    4,sp
        inc_gr_immed    4,sp
        set_gr_immed    -1,gr7
        set_gr_immed    -1,gr7
        cldsb           @(sp,gr7),gr8,cc5,0
        cldsb           @(sp,gr7),gr8,cc5,0
        test_gr_immed   0,gr8
        test_gr_immed   0,gr8
        set_mem_limmed  0xdead,0xbeef,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_gr_limmed   0xbeef,0xdead,gr8
        set_gr_limmed   0xbeef,0xdead,gr8
        set_gr_immed    0,gr7
        set_gr_immed    0,gr7
        cldsb           @(sp,gr7),gr8,cc1,1
        cldsb           @(sp,gr7),gr8,cc1,1
        test_gr_limmed  0xbeef,0xdead,gr8
        test_gr_limmed  0xbeef,0xdead,gr8
        set_gr_immed    1,gr7
        set_gr_immed    1,gr7
        cldsb           @(sp,gr7),gr8,cc1,1
        cldsb           @(sp,gr7),gr8,cc1,1
        test_gr_limmed  0xbeef,0xdead,gr8
        test_gr_limmed  0xbeef,0xdead,gr8
        set_mem_limmed  0xffff,0xff00,sp
        set_mem_limmed  0xffff,0xff00,sp
        inc_gr_immed    4,sp
        inc_gr_immed    4,sp
        set_gr_immed    -1,gr7
        set_gr_immed    -1,gr7
        cldsb           @(sp,gr7),gr8,cc5,1
        cldsb           @(sp,gr7),gr8,cc5,1
        test_gr_limmed  0xbeef,0xdead,gr8
        test_gr_limmed  0xbeef,0xdead,gr8
        set_mem_limmed  0xdead,0xbeef,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_gr_limmed   0xbeef,0xdead,gr8
        set_gr_limmed   0xbeef,0xdead,gr8
        set_gr_immed    0,gr7
        set_gr_immed    0,gr7
        cldsb           @(sp,gr7),gr8,cc2,0
        cldsb           @(sp,gr7),gr8,cc2,0
        test_gr_limmed  0xbeef,0xdead,gr8
        test_gr_limmed  0xbeef,0xdead,gr8
        set_gr_immed    1,gr7
        set_gr_immed    1,gr7
        cldsb           @(sp,gr7),gr8,cc2,0
        cldsb           @(sp,gr7),gr8,cc2,0
        test_gr_limmed  0xbeef,0xdead,gr8
        test_gr_limmed  0xbeef,0xdead,gr8
        set_mem_limmed  0xffff,0xff00,sp
        set_mem_limmed  0xffff,0xff00,sp
        inc_gr_immed    4,sp
        inc_gr_immed    4,sp
        set_gr_immed    -1,gr7
        set_gr_immed    -1,gr7
        cldsb           @(sp,gr7),gr8,cc6,1
        cldsb           @(sp,gr7),gr8,cc6,1
        test_gr_limmed  0xbeef,0xdead,gr8
        test_gr_limmed  0xbeef,0xdead,gr8
        set_mem_limmed  0xdead,0xbeef,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_gr_limmed   0xbeef,0xdead,gr8
        set_gr_limmed   0xbeef,0xdead,gr8
        set_gr_immed    0,gr7
        set_gr_immed    0,gr7
        cldsb           @(sp,gr7),gr8,cc3,0
        cldsb           @(sp,gr7),gr8,cc3,0
        test_gr_limmed  0xbeef,0xdead,gr8
        test_gr_limmed  0xbeef,0xdead,gr8
        set_gr_immed    1,gr7
        set_gr_immed    1,gr7
        cldsb           @(sp,gr7),gr8,cc3,0
        cldsb           @(sp,gr7),gr8,cc3,0
        test_gr_limmed  0xbeef,0xdead,gr8
        test_gr_limmed  0xbeef,0xdead,gr8
        set_mem_limmed  0xffff,0xff00,sp
        set_mem_limmed  0xffff,0xff00,sp
        inc_gr_immed    4,sp
        inc_gr_immed    4,sp
        set_gr_immed    -1,gr7
        set_gr_immed    -1,gr7
        cldsb           @(sp,gr7),gr8,cc7,1
        cldsb           @(sp,gr7),gr8,cc7,1
        test_gr_limmed  0xbeef,0xdead,gr8
        test_gr_limmed  0xbeef,0xdead,gr8
        pass
        pass
 
 

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