OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [frv/] [cmsubhus.cgs] - Diff between revs 24 and 33

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 24	Rev 33
`# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond`	`# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond`
`# mach: frv fr500 fr400`	`# mach: frv fr500 fr400`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`

`.global cmsubhus`	`.global cmsubhus`
`cmsubhus:`	`cmsubhus:`
`set_spr_immed 0x1b1b,cccr`	`set_spr_immed 0x1b1b,cccr`

`set_fr_iimmed 0x0000,0x0000,fr10`	`set_fr_iimmed 0x0000,0x0000,fr10`
`set_fr_iimmed 0x0000,0x0000,fr11`	`set_fr_iimmed 0x0000,0x0000,fr11`
`cmsubhus fr10,fr11,fr12,cc0,1`	`cmsubhus fr10,fr11,fr12,cc0,1`
`test_fr_limmed 0x0000,0x0000,fr12`	`test_fr_limmed 0x0000,0x0000,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0xdead,0xbeef,fr10`	`set_fr_iimmed 0xdead,0xbeef,fr10`
`set_fr_iimmed 0x0000,0x0000,fr11`	`set_fr_iimmed 0x0000,0x0000,fr11`
`cmsubhus fr10,fr11,fr12,cc0,1`	`cmsubhus fr10,fr11,fr12,cc0,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x1234,0x5678,fr10`	`set_fr_iimmed 0x1234,0x5678,fr10`
`set_fr_iimmed 0x1111,0x1111,fr11`	`set_fr_iimmed 0x1111,0x1111,fr11`
`cmsubhus fr10,fr11,fr12,cc0,1`	`cmsubhus fr10,fr11,fr12,cc0,1`
`test_fr_limmed 0x0123,0x4567,fr12`	`test_fr_limmed 0x0123,0x4567,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x7ffe,0x7ffe,fr10`	`set_fr_iimmed 0x7ffe,0x7ffe,fr10`
`set_fr_iimmed 0x0002,0x0001,fr11`	`set_fr_iimmed 0x0002,0x0001,fr11`
`cmsubhus fr10,fr11,fr12,cc0,1`	`cmsubhus fr10,fr11,fr12,cc0,1`
`test_fr_limmed 0x7ffc,0x7ffd,fr12`	`test_fr_limmed 0x7ffc,0x7ffd,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0001,0x0002,fr11`	`set_fr_iimmed 0x0001,0x0002,fr11`
`cmsubhus fr10,fr11,fr12,cc4,1`	`cmsubhus fr10,fr11,fr12,cc4,1`
`test_fr_limmed 0x0000,0x0000,fr12`	`test_fr_limmed 0x0000,0x0000,fr12`
`test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set`	`test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set`
`test_spr_bits 2,1,1,msr0 ; msr0.ovf set`	`test_spr_bits 2,1,1,msr0 ; msr0.ovf set`
`test_spr_bits 1,0,1,msr0 ; msr0.aovf set`	`test_spr_bits 1,0,1,msr0 ; msr0.aovf set`
`test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set`	`test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set`

`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0002,0x0001,fr11`	`set_fr_iimmed 0x0002,0x0001,fr11`
`cmsubhus fr10,fr11,fr12,cc4,1`	`cmsubhus fr10,fr11,fr12,cc4,1`
`test_fr_limmed 0x0000,0x0000,fr12`	`test_fr_limmed 0x0000,0x0000,fr12`
`test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set`	`test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set`
`test_spr_bits 2,1,1,msr0 ; msr0.ovf set`	`test_spr_bits 2,1,1,msr0 ; msr0.ovf set`
`test_spr_bits 1,0,1,msr0 ; msr0.aovf set`	`test_spr_bits 1,0,1,msr0 ; msr0.aovf set`
`test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set`	`test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set`

`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_spr_immed 0,msr1`	`set_spr_immed 0,msr1`
`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0002,0x0002,fr11`	`set_fr_iimmed 0x0002,0x0002,fr11`
`cmsubhus.p fr10,fr10,fr12,cc4,1`	`cmsubhus.p fr10,fr10,fr12,cc4,1`
`cmsubhus fr10,fr11,fr13,cc4,1`	`cmsubhus fr10,fr11,fr13,cc4,1`
`test_fr_limmed 0x0000,0x0000,fr12`	`test_fr_limmed 0x0000,0x0000,fr12`
`test_fr_limmed 0x0000,0x0000,fr13`	`test_fr_limmed 0x0000,0x0000,fr13`
`test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set`	`test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set`
`test_spr_bits 2,1,1,msr1 ; msr1.ovf set`	`test_spr_bits 2,1,1,msr1 ; msr1.ovf set`
`test_spr_bits 1,0,1,msr0 ; msr0.aovf set`	`test_spr_bits 1,0,1,msr0 ; msr0.aovf set`
`test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set`	`test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set`

`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_spr_immed 0,msr1`	`set_spr_immed 0,msr1`
`set_fr_iimmed 0x0000,0x0000,fr10`	`set_fr_iimmed 0x0000,0x0000,fr10`
`set_fr_iimmed 0x0000,0x0000,fr11`	`set_fr_iimmed 0x0000,0x0000,fr11`
`cmsubhus fr10,fr11,fr12,cc1,0`	`cmsubhus fr10,fr11,fr12,cc1,0`
`test_fr_limmed 0x0000,0x0000,fr12`	`test_fr_limmed 0x0000,0x0000,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0xdead,0xbeef,fr10`	`set_fr_iimmed 0xdead,0xbeef,fr10`
`set_fr_iimmed 0x0000,0x0000,fr11`	`set_fr_iimmed 0x0000,0x0000,fr11`
`cmsubhus fr10,fr11,fr12,cc1,0`	`cmsubhus fr10,fr11,fr12,cc1,0`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x1234,0x5678,fr10`	`set_fr_iimmed 0x1234,0x5678,fr10`
`set_fr_iimmed 0x1111,0x1111,fr11`	`set_fr_iimmed 0x1111,0x1111,fr11`
`cmsubhus fr10,fr11,fr12,cc1,0`	`cmsubhus fr10,fr11,fr12,cc1,0`
`test_fr_limmed 0x0123,0x4567,fr12`	`test_fr_limmed 0x0123,0x4567,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x7ffe,0x7ffe,fr10`	`set_fr_iimmed 0x7ffe,0x7ffe,fr10`
`set_fr_iimmed 0x0002,0x0001,fr11`	`set_fr_iimmed 0x0002,0x0001,fr11`
`cmsubhus fr10,fr11,fr12,cc1,0`	`cmsubhus fr10,fr11,fr12,cc1,0`
`test_fr_limmed 0x7ffc,0x7ffd,fr12`	`test_fr_limmed 0x7ffc,0x7ffd,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0001,0x0002,fr11`	`set_fr_iimmed 0x0001,0x0002,fr11`
`cmsubhus fr10,fr11,fr12,cc5,0`	`cmsubhus fr10,fr11,fr12,cc5,0`
`test_fr_limmed 0x0000,0x0000,fr12`	`test_fr_limmed 0x0000,0x0000,fr12`
`test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set`	`test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set`
`test_spr_bits 2,1,1,msr0 ; msr0.ovf set`	`test_spr_bits 2,1,1,msr0 ; msr0.ovf set`
`test_spr_bits 1,0,1,msr0 ; msr0.aovf set`	`test_spr_bits 1,0,1,msr0 ; msr0.aovf set`
`test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set`	`test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set`

`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0002,0x0001,fr11`	`set_fr_iimmed 0x0002,0x0001,fr11`
`cmsubhus fr10,fr11,fr12,cc5,0`	`cmsubhus fr10,fr11,fr12,cc5,0`
`test_fr_limmed 0x0000,0x0000,fr12`	`test_fr_limmed 0x0000,0x0000,fr12`
`test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set`	`test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set`
`test_spr_bits 2,1,1,msr0 ; msr0.ovf set`	`test_spr_bits 2,1,1,msr0 ; msr0.ovf set`
`test_spr_bits 1,0,1,msr0 ; msr0.aovf set`	`test_spr_bits 1,0,1,msr0 ; msr0.aovf set`
`test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set`	`test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set`

`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_spr_immed 0,msr1`	`set_spr_immed 0,msr1`
`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0002,0x0002,fr11`	`set_fr_iimmed 0x0002,0x0002,fr11`
`cmsubhus.p fr10,fr10,fr12,cc5,0`	`cmsubhus.p fr10,fr10,fr12,cc5,0`
`cmsubhus fr10,fr11,fr13,cc5,0`	`cmsubhus fr10,fr11,fr13,cc5,0`
`test_fr_limmed 0x0000,0x0000,fr12`	`test_fr_limmed 0x0000,0x0000,fr12`
`test_fr_limmed 0x0000,0x0000,fr13`	`test_fr_limmed 0x0000,0x0000,fr13`
`test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set`	`test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set`
`test_spr_bits 2,1,1,msr1 ; msr1.ovf set`	`test_spr_bits 2,1,1,msr1 ; msr1.ovf set`
`test_spr_bits 1,0,1,msr0 ; msr0.aovf set`	`test_spr_bits 1,0,1,msr0 ; msr0.aovf set`
`test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set`	`test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set`

`set_fr_iimmed 0xdead,0xbeef,fr12`	`set_fr_iimmed 0xdead,0xbeef,fr12`
`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_spr_immed 0,msr1`	`set_spr_immed 0,msr1`
`set_fr_iimmed 0x0000,0x0000,fr10`	`set_fr_iimmed 0x0000,0x0000,fr10`
`set_fr_iimmed 0x0000,0x0000,fr11`	`set_fr_iimmed 0x0000,0x0000,fr11`
`cmsubhus fr10,fr11,fr12,cc0,0`	`cmsubhus fr10,fr11,fr12,cc0,0`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0xbeef,0xdead,fr10`	`set_fr_iimmed 0xbeef,0xdead,fr10`
`set_fr_iimmed 0x0000,0x0000,fr11`	`set_fr_iimmed 0x0000,0x0000,fr11`
`cmsubhus fr10,fr11,fr12,cc0,0`	`cmsubhus fr10,fr11,fr12,cc0,0`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x1234,0x5678,fr10`	`set_fr_iimmed 0x1234,0x5678,fr10`
`set_fr_iimmed 0x1111,0x1111,fr11`	`set_fr_iimmed 0x1111,0x1111,fr11`
`cmsubhus fr10,fr11,fr12,cc0,0`	`cmsubhus fr10,fr11,fr12,cc0,0`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x7ffe,0x7ffe,fr10`	`set_fr_iimmed 0x7ffe,0x7ffe,fr10`
`set_fr_iimmed 0x0002,0x0001,fr11`	`set_fr_iimmed 0x0002,0x0001,fr11`
`cmsubhus fr10,fr11,fr12,cc0,0`	`cmsubhus fr10,fr11,fr12,cc0,0`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0001,0x0002,fr11`	`set_fr_iimmed 0x0001,0x0002,fr11`
`cmsubhus fr10,fr11,fr12,cc4,0`	`cmsubhus fr10,fr11,fr12,cc4,0`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0002,0x0001,fr11`	`set_fr_iimmed 0x0002,0x0001,fr11`
`cmsubhus fr10,fr11,fr12,cc4,0`	`cmsubhus fr10,fr11,fr12,cc4,0`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0xbeef,0xdead,fr13`	`set_fr_iimmed 0xbeef,0xdead,fr13`
`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_spr_immed 0,msr1`	`set_spr_immed 0,msr1`
`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0002,0x0002,fr11`	`set_fr_iimmed 0x0002,0x0002,fr11`
`cmsubhus.p fr10,fr10,fr12,cc4,0`	`cmsubhus.p fr10,fr10,fr12,cc4,0`
`cmsubhus fr10,fr11,fr13,cc4,0`	`cmsubhus fr10,fr11,fr13,cc4,0`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_fr_limmed 0xbeef,0xdead,fr13`	`test_fr_limmed 0xbeef,0xdead,fr13`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0xdead,0xbeef,fr12`	`set_fr_iimmed 0xdead,0xbeef,fr12`
`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_spr_immed 0,msr1`	`set_spr_immed 0,msr1`
`set_fr_iimmed 0x0000,0x0000,fr10`	`set_fr_iimmed 0x0000,0x0000,fr10`
`set_fr_iimmed 0x0000,0x0000,fr11`	`set_fr_iimmed 0x0000,0x0000,fr11`
`cmsubhus fr10,fr11,fr12,cc1,1`	`cmsubhus fr10,fr11,fr12,cc1,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0xbeef,0xdead,fr10`	`set_fr_iimmed 0xbeef,0xdead,fr10`
`set_fr_iimmed 0x0000,0x0000,fr11`	`set_fr_iimmed 0x0000,0x0000,fr11`
`cmsubhus fr10,fr11,fr12,cc1,1`	`cmsubhus fr10,fr11,fr12,cc1,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x1234,0x5678,fr10`	`set_fr_iimmed 0x1234,0x5678,fr10`
`set_fr_iimmed 0x1111,0x1111,fr11`	`set_fr_iimmed 0x1111,0x1111,fr11`
`cmsubhus fr10,fr11,fr12,cc1,1`	`cmsubhus fr10,fr11,fr12,cc1,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x7ffe,0x7ffe,fr10`	`set_fr_iimmed 0x7ffe,0x7ffe,fr10`
`set_fr_iimmed 0x0002,0x0001,fr11`	`set_fr_iimmed 0x0002,0x0001,fr11`
`cmsubhus fr10,fr11,fr12,cc1,1`	`cmsubhus fr10,fr11,fr12,cc1,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0001,0x0002,fr11`	`set_fr_iimmed 0x0001,0x0002,fr11`
`cmsubhus fr10,fr11,fr12,cc5,1`	`cmsubhus fr10,fr11,fr12,cc5,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0002,0x0001,fr11`	`set_fr_iimmed 0x0002,0x0001,fr11`
`cmsubhus fr10,fr11,fr12,cc5,1`	`cmsubhus fr10,fr11,fr12,cc5,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0xbeef,0xdead,fr13`	`set_fr_iimmed 0xbeef,0xdead,fr13`
`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_spr_immed 0,msr1`	`set_spr_immed 0,msr1`
`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0002,0x0002,fr11`	`set_fr_iimmed 0x0002,0x0002,fr11`
`cmsubhus.p fr10,fr10,fr12,cc5,1`	`cmsubhus.p fr10,fr10,fr12,cc5,1`
`cmsubhus fr10,fr11,fr13,cc5,1`	`cmsubhus fr10,fr11,fr13,cc5,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_fr_limmed 0xbeef,0xdead,fr13`	`test_fr_limmed 0xbeef,0xdead,fr13`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0xdead,0xbeef,fr12`	`set_fr_iimmed 0xdead,0xbeef,fr12`
`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_spr_immed 0,msr1`	`set_spr_immed 0,msr1`
`set_fr_iimmed 0x0000,0x0000,fr10`	`set_fr_iimmed 0x0000,0x0000,fr10`
`set_fr_iimmed 0x0000,0x0000,fr11`	`set_fr_iimmed 0x0000,0x0000,fr11`
`cmsubhus fr10,fr11,fr12,cc2,0`	`cmsubhus fr10,fr11,fr12,cc2,0`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0xbeef,0xdead,fr10`	`set_fr_iimmed 0xbeef,0xdead,fr10`
`set_fr_iimmed 0x0000,0x0000,fr11`	`set_fr_iimmed 0x0000,0x0000,fr11`
`cmsubhus fr10,fr11,fr12,cc2,1`	`cmsubhus fr10,fr11,fr12,cc2,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x1234,0x5678,fr10`	`set_fr_iimmed 0x1234,0x5678,fr10`
`set_fr_iimmed 0x1111,0x1111,fr11`	`set_fr_iimmed 0x1111,0x1111,fr11`
`cmsubhus fr10,fr11,fr12,cc2,0`	`cmsubhus fr10,fr11,fr12,cc2,0`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x7ffe,0x7ffe,fr10`	`set_fr_iimmed 0x7ffe,0x7ffe,fr10`
`set_fr_iimmed 0x0002,0x0001,fr11`	`set_fr_iimmed 0x0002,0x0001,fr11`
`cmsubhus fr10,fr11,fr12,cc2,1`	`cmsubhus fr10,fr11,fr12,cc2,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0001,0x0002,fr11`	`set_fr_iimmed 0x0001,0x0002,fr11`
`cmsubhus fr10,fr11,fr12,cc6,0`	`cmsubhus fr10,fr11,fr12,cc6,0`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0002,0x0001,fr11`	`set_fr_iimmed 0x0002,0x0001,fr11`
`cmsubhus fr10,fr11,fr12,cc6,1`	`cmsubhus fr10,fr11,fr12,cc6,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0xbeef,0xdead,fr13`	`set_fr_iimmed 0xbeef,0xdead,fr13`
`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_spr_immed 0,msr1`	`set_spr_immed 0,msr1`
`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0002,0x0002,fr11`	`set_fr_iimmed 0x0002,0x0002,fr11`
`cmsubhus.p fr10,fr10,fr12,cc6,0`	`cmsubhus.p fr10,fr10,fr12,cc6,0`
`cmsubhus fr10,fr11,fr13,cc6,1`	`cmsubhus fr10,fr11,fr13,cc6,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_fr_limmed 0xbeef,0xdead,fr13`	`test_fr_limmed 0xbeef,0xdead,fr13`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`
`;`	`;`
`set_fr_iimmed 0xdead,0xbeef,fr12`	`set_fr_iimmed 0xdead,0xbeef,fr12`
`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_spr_immed 0,msr1`	`set_spr_immed 0,msr1`
`set_fr_iimmed 0x0000,0x0000,fr10`	`set_fr_iimmed 0x0000,0x0000,fr10`
`set_fr_iimmed 0x0000,0x0000,fr11`	`set_fr_iimmed 0x0000,0x0000,fr11`
`cmsubhus fr10,fr11,fr12,cc3,0`	`cmsubhus fr10,fr11,fr12,cc3,0`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0xbeef,0xdead,fr10`	`set_fr_iimmed 0xbeef,0xdead,fr10`
`set_fr_iimmed 0x0000,0x0000,fr11`	`set_fr_iimmed 0x0000,0x0000,fr11`
`cmsubhus fr10,fr11,fr12,cc3,1`	`cmsubhus fr10,fr11,fr12,cc3,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x1234,0x5678,fr10`	`set_fr_iimmed 0x1234,0x5678,fr10`
`set_fr_iimmed 0x1111,0x1111,fr11`	`set_fr_iimmed 0x1111,0x1111,fr11`
`cmsubhus fr10,fr11,fr12,cc3,0`	`cmsubhus fr10,fr11,fr12,cc3,0`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x7ffe,0x7ffe,fr10`	`set_fr_iimmed 0x7ffe,0x7ffe,fr10`
`set_fr_iimmed 0x0002,0x0001,fr11`	`set_fr_iimmed 0x0002,0x0001,fr11`
`cmsubhus fr10,fr11,fr12,cc3,1`	`cmsubhus fr10,fr11,fr12,cc3,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0001,0x0002,fr11`	`set_fr_iimmed 0x0001,0x0002,fr11`
`cmsubhus fr10,fr11,fr12,cc7,0`	`cmsubhus fr10,fr11,fr12,cc7,0`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0002,0x0001,fr11`	`set_fr_iimmed 0x0002,0x0001,fr11`
`cmsubhus fr10,fr11,fr12,cc7,1`	`cmsubhus fr10,fr11,fr12,cc7,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`set_fr_iimmed 0xbeef,0xdead,fr13`	`set_fr_iimmed 0xbeef,0xdead,fr13`
`set_spr_immed 0,msr0`	`set_spr_immed 0,msr0`
`set_spr_immed 0,msr1`	`set_spr_immed 0,msr1`
`set_fr_iimmed 0x0001,0x0001,fr10`	`set_fr_iimmed 0x0001,0x0001,fr10`
`set_fr_iimmed 0x0002,0x0002,fr11`	`set_fr_iimmed 0x0002,0x0002,fr11`
`cmsubhus.p fr10,fr10,fr12,cc7,0`	`cmsubhus.p fr10,fr10,fr12,cc7,0`
`cmsubhus fr10,fr11,fr13,cc7,1`	`cmsubhus fr10,fr11,fr13,cc7,1`
`test_fr_limmed 0xdead,0xbeef,fr12`	`test_fr_limmed 0xdead,0xbeef,fr12`
`test_fr_limmed 0xbeef,0xdead,fr13`	`test_fr_limmed 0xbeef,0xdead,fr13`
`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`	`test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear`
`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`	`test_spr_bits 2,1,0,msr0 ; msr0.ovf not set`
`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`	`test_spr_bits 1,0,0,msr0 ; msr0.aovf not set`
`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`	`test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set`

`pass`	`pass`

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.