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Rev 33 |
# frv testcase for fbgelr $FCCi,$hint
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# frv testcase for fbgelr $FCCi,$hint
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# mach: all
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# mach: all
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global fbgelr
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.global fbgelr
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fbgelr:
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fbgelr:
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x0 0
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set_fcc 0x0 0
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fbgelr fcc0,0
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fbgelr fcc0,0
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x1 1
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set_fcc 0x1 1
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fbgelr fcc1,1
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fbgelr fcc1,1
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set_spr_addr ok3,lr
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set_spr_addr ok3,lr
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set_fcc 0x2 2
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set_fcc 0x2 2
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fbgelr fcc2,2
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fbgelr fcc2,2
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fail
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fail
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ok3:
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ok3:
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set_spr_addr ok4,lr
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set_spr_addr ok4,lr
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set_fcc 0x3 3
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set_fcc 0x3 3
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fbgelr fcc3,3
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fbgelr fcc3,3
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fail
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fail
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ok4:
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ok4:
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x4 0
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set_fcc 0x4 0
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fbgelr fcc0,0
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fbgelr fcc0,0
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x5 1
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set_fcc 0x5 1
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fbgelr fcc1,1
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fbgelr fcc1,1
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set_spr_addr ok7,lr
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set_spr_addr ok7,lr
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set_fcc 0x6 2
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set_fcc 0x6 2
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fbgelr fcc2,2
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fbgelr fcc2,2
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fail
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fail
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ok7:
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ok7:
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set_spr_addr ok8,lr
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set_spr_addr ok8,lr
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set_fcc 0x7 3
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set_fcc 0x7 3
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fbgelr fcc3,3
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fbgelr fcc3,3
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fail
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fail
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ok8:
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ok8:
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set_spr_addr ok9,lr
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set_spr_addr ok9,lr
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set_fcc 0x8 0
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set_fcc 0x8 0
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fbgelr fcc0,0
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fbgelr fcc0,0
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fail
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fail
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ok9:
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ok9:
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set_spr_addr oka,lr
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set_spr_addr oka,lr
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set_fcc 0x9 1
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set_fcc 0x9 1
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fbgelr fcc1,1
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fbgelr fcc1,1
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fail
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fail
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oka:
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oka:
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set_spr_addr okb,lr
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set_spr_addr okb,lr
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set_fcc 0xa 2
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set_fcc 0xa 2
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fbgelr fcc2,2
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fbgelr fcc2,2
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fail
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fail
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okb:
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okb:
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set_spr_addr okc,lr
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set_spr_addr okc,lr
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set_fcc 0xb 3
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set_fcc 0xb 3
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fbgelr fcc3,3
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fbgelr fcc3,3
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fail
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fail
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okc:
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okc:
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set_spr_addr okd,lr
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set_spr_addr okd,lr
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set_fcc 0xc 0
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set_fcc 0xc 0
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fbgelr fcc0,0
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fbgelr fcc0,0
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fail
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fail
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okd:
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okd:
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set_spr_addr oke,lr
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set_spr_addr oke,lr
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set_fcc 0xd 1
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set_fcc 0xd 1
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fbgelr fcc1,1
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fbgelr fcc1,1
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fail
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fail
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oke:
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oke:
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set_spr_addr okf,lr
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set_spr_addr okf,lr
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set_fcc 0xe 2
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set_fcc 0xe 2
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fbgelr fcc2,2
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fbgelr fcc2,2
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fail
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fail
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okf:
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okf:
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set_spr_addr okg,lr
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set_spr_addr okg,lr
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set_fcc 0xf 3
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set_fcc 0xf 3
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fbgelr fcc3,3
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fbgelr fcc3,3
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fail
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fail
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okg:
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okg:
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pass
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pass
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bad:
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bad:
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fail
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fail
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