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[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [frv/] [fbnelr.cgs] - Diff between revs 24 and 33

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Rev 24 Rev 33
# frv testcase for fbnelr $FCCi,$hint
# frv testcase for fbnelr $FCCi,$hint
# mach: all
# mach: all
        .include "testutils.inc"
        .include "testutils.inc"
        start
        start
        .global fbnelr
        .global fbnelr
fbnelr:
fbnelr:
        set_spr_addr    bad,lr
        set_spr_addr    bad,lr
        set_fcc         0x0 0
        set_fcc         0x0 0
        fbnelr          fcc0,0
        fbnelr          fcc0,0
        set_spr_addr    ok2,lr
        set_spr_addr    ok2,lr
        set_fcc         0x1 1
        set_fcc         0x1 1
        fbnelr          fcc1,1
        fbnelr          fcc1,1
        fail
        fail
ok2:
ok2:
        set_spr_addr    ok3,lr
        set_spr_addr    ok3,lr
        set_fcc         0x2 2
        set_fcc         0x2 2
        fbnelr          fcc2,2
        fbnelr          fcc2,2
        fail
        fail
ok3:
ok3:
        set_spr_addr    ok4,lr
        set_spr_addr    ok4,lr
        set_fcc         0x3 3
        set_fcc         0x3 3
        fbnelr          fcc3,3
        fbnelr          fcc3,3
        fail
        fail
ok4:
ok4:
        set_spr_addr    ok5,lr
        set_spr_addr    ok5,lr
        set_fcc         0x4 0
        set_fcc         0x4 0
        fbnelr          fcc0,0
        fbnelr          fcc0,0
        fail
        fail
ok5:
ok5:
        set_spr_addr    ok6,lr
        set_spr_addr    ok6,lr
        set_fcc         0x5 1
        set_fcc         0x5 1
        fbnelr          fcc1,1
        fbnelr          fcc1,1
        fail
        fail
ok6:
ok6:
        set_spr_addr    ok7,lr
        set_spr_addr    ok7,lr
        set_fcc         0x6 2
        set_fcc         0x6 2
        fbnelr          fcc2,2
        fbnelr          fcc2,2
        fail
        fail
ok7:
ok7:
        set_spr_addr    ok8,lr
        set_spr_addr    ok8,lr
        set_fcc         0x7 3
        set_fcc         0x7 3
        fbnelr          fcc3,3
        fbnelr          fcc3,3
        fail
        fail
ok8:
ok8:
        set_spr_addr    bad,lr
        set_spr_addr    bad,lr
        set_fcc         0x8 0
        set_fcc         0x8 0
        fbnelr          fcc0,0
        fbnelr          fcc0,0
        set_spr_addr    oka,lr
        set_spr_addr    oka,lr
        set_fcc         0x9 1
        set_fcc         0x9 1
        fbnelr          fcc1,1
        fbnelr          fcc1,1
        fail
        fail
oka:
oka:
        set_spr_addr    okb,lr
        set_spr_addr    okb,lr
        set_fcc         0xa 2
        set_fcc         0xa 2
        fbnelr          fcc2,2
        fbnelr          fcc2,2
        fail
        fail
okb:
okb:
        set_spr_addr    okc,lr
        set_spr_addr    okc,lr
        set_fcc         0xb 3
        set_fcc         0xb 3
        fbnelr          fcc3,3
        fbnelr          fcc3,3
        fail
        fail
okc:
okc:
        set_spr_addr    okd,lr
        set_spr_addr    okd,lr
        set_fcc         0xc 0
        set_fcc         0xc 0
        fbnelr          fcc0,0
        fbnelr          fcc0,0
        fail
        fail
okd:
okd:
        set_spr_addr    oke,lr
        set_spr_addr    oke,lr
        set_fcc         0xd 1
        set_fcc         0xd 1
        fbnelr          fcc1,1
        fbnelr          fcc1,1
        fail
        fail
oke:
oke:
        set_spr_addr    okf,lr
        set_spr_addr    okf,lr
        set_fcc         0xe 2
        set_fcc         0xe 2
        fbnelr          fcc2,2
        fbnelr          fcc2,2
        fail
        fail
okf:
okf:
        set_spr_addr    okg,lr
        set_spr_addr    okg,lr
        set_fcc         0xf 3
        set_fcc         0xf 3
        fbnelr          fcc3,3
        fbnelr          fcc3,3
        fail
        fail
okg:
okg:
        pass
        pass
bad:
bad:
        fail
        fail
 
 

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