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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
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Rev 33 |
# frv testcase for fcbgtlr $FCCi,$ccond,$hint
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# frv testcase for fcbgtlr $FCCi,$ccond,$hint
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# mach: all
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# mach: all
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global fcbgtlr
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.global fcbgtlr
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fcbgtlr:
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fcbgtlr:
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; ccond is true
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; ccond is true
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set_spr_immed 128,lcr
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set_spr_immed 128,lcr
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x0 0
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set_fcc 0x0 0
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fcbgtlr fcc0,0,0
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fcbgtlr fcc0,0,0
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x1 1
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set_fcc 0x1 1
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fcbgtlr fcc1,0,1
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fcbgtlr fcc1,0,1
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set_spr_addr ok3,lr
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set_spr_addr ok3,lr
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set_fcc 0x2 2
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set_fcc 0x2 2
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fcbgtlr fcc2,0,2
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fcbgtlr fcc2,0,2
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fail
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fail
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ok3:
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ok3:
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set_spr_addr ok4,lr
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set_spr_addr ok4,lr
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set_fcc 0x3 3
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set_fcc 0x3 3
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fcbgtlr fcc3,0,3
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fcbgtlr fcc3,0,3
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fail
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fail
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ok4:
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ok4:
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x4 0
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set_fcc 0x4 0
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fcbgtlr fcc0,0,0
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fcbgtlr fcc0,0,0
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x5 1
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set_fcc 0x5 1
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fcbgtlr fcc1,0,1
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fcbgtlr fcc1,0,1
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set_spr_addr ok7,lr
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set_spr_addr ok7,lr
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set_fcc 0x6 2
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set_fcc 0x6 2
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fcbgtlr fcc2,0,2
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fcbgtlr fcc2,0,2
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fail
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fail
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ok7:
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ok7:
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set_spr_addr ok8,lr
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set_spr_addr ok8,lr
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set_fcc 0x7 3
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set_fcc 0x7 3
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fcbgtlr fcc3,0,3
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fcbgtlr fcc3,0,3
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fail
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fail
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ok8:
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ok8:
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x8 0
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set_fcc 0x8 0
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fcbgtlr fcc0,0,0
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fcbgtlr fcc0,0,0
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x9 1
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set_fcc 0x9 1
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fcbgtlr fcc1,0,1
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fcbgtlr fcc1,0,1
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set_spr_addr okb,lr
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set_spr_addr okb,lr
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set_fcc 0xa 2
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set_fcc 0xa 2
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fcbgtlr fcc2,0,2
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fcbgtlr fcc2,0,2
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fail
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fail
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okb:
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okb:
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set_spr_addr okc,lr
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set_spr_addr okc,lr
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set_fcc 0xb 3
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set_fcc 0xb 3
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fcbgtlr fcc3,0,3
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fcbgtlr fcc3,0,3
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fail
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fail
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okc:
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okc:
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0xc 0
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set_fcc 0xc 0
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fcbgtlr fcc0,0,0
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fcbgtlr fcc0,0,0
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0xd 1
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set_fcc 0xd 1
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fcbgtlr fcc1,0,1
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fcbgtlr fcc1,0,1
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set_spr_addr okf,lr
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set_spr_addr okf,lr
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set_fcc 0xe 2
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set_fcc 0xe 2
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fcbgtlr fcc2,0,2
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fcbgtlr fcc2,0,2
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fail
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fail
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okf:
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okf:
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set_spr_addr okg,lr
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set_spr_addr okg,lr
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set_fcc 0xf 3
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set_fcc 0xf 3
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fcbgtlr fcc3,0,3
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fcbgtlr fcc3,0,3
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fail
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fail
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okg:
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okg:
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; ccond is true
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; ccond is true
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x0 0
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set_fcc 0x0 0
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fcbgtlr fcc0,1,0
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fcbgtlr fcc0,1,0
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x1 1
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set_fcc 0x1 1
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fcbgtlr fcc1,1,1
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fcbgtlr fcc1,1,1
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr okj,lr
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set_spr_addr okj,lr
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set_fcc 0x2 2
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set_fcc 0x2 2
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fcbgtlr fcc2,1,2
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fcbgtlr fcc2,1,2
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fail
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fail
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okj:
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okj:
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr okk,lr
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set_spr_addr okk,lr
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set_fcc 0x3 3
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set_fcc 0x3 3
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fcbgtlr fcc3,1,3
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fcbgtlr fcc3,1,3
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fail
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fail
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okk:
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okk:
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x4 0
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set_fcc 0x4 0
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fcbgtlr fcc0,1,0
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fcbgtlr fcc0,1,0
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x5 1
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set_fcc 0x5 1
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fcbgtlr fcc1,1,1
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fcbgtlr fcc1,1,1
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr okn,lr
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set_spr_addr okn,lr
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set_fcc 0x6 2
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set_fcc 0x6 2
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fcbgtlr fcc2,1,2
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fcbgtlr fcc2,1,2
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fail
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fail
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okn:
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okn:
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr oko,lr
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set_spr_addr oko,lr
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set_fcc 0x7 3
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set_fcc 0x7 3
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fcbgtlr fcc3,1,3
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fcbgtlr fcc3,1,3
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fail
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fail
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oko:
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oko:
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x8 0
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set_fcc 0x8 0
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fcbgtlr fcc0,1,0
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fcbgtlr fcc0,1,0
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0x9 1
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set_fcc 0x9 1
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fcbgtlr fcc1,1,1
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fcbgtlr fcc1,1,1
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr okr,lr
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set_spr_addr okr,lr
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set_fcc 0xa 2
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set_fcc 0xa 2
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fcbgtlr fcc2,1,2
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fcbgtlr fcc2,1,2
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fail
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fail
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okr:
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okr:
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr oks,lr
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set_spr_addr oks,lr
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set_fcc 0xb 3
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set_fcc 0xb 3
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fcbgtlr fcc3,1,3
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fcbgtlr fcc3,1,3
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fail
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fail
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oks:
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oks:
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0xc 0
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set_fcc 0xc 0
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fcbgtlr fcc0,1,0
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fcbgtlr fcc0,1,0
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr bad,lr
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set_spr_addr bad,lr
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set_fcc 0xd 1
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set_fcc 0xd 1
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fcbgtlr fcc1,1,1
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fcbgtlr fcc1,1,1
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr okv,lr
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set_spr_addr okv,lr
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set_fcc 0xe 2
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set_fcc 0xe 2
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fcbgtlr fcc2,1,2
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fcbgtlr fcc2,1,2
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fail
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fail
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okv:
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okv:
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_spr_addr okw,lr
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set_spr_addr okw,lr
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set_fcc 0xf 3
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set_fcc 0xf 3
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fcbgtlr fcc3,1,3
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fcbgtlr fcc3,1,3
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fail
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fail
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okw:
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okw:
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; ccond is false
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; ccond is false
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set_spr_immed 128,lcr
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set_spr_immed 128,lcr
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set_fcc 0x0 0
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set_fcc 0x0 0
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fcbgtlr fcc0,1,0
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fcbgtlr fcc0,1,0
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set_fcc 0x1 1
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set_fcc 0x1 1
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fcbgtlr fcc1,1,1
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fcbgtlr fcc1,1,1
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set_fcc 0x2 2
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set_fcc 0x2 2
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fcbgtlr fcc2,1,2
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fcbgtlr fcc2,1,2
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set_fcc 0x3 3
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set_fcc 0x3 3
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fcbgtlr fcc3,1,3
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fcbgtlr fcc3,1,3
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set_fcc 0x4 0
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set_fcc 0x4 0
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fcbgtlr fcc0,1,0
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fcbgtlr fcc0,1,0
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set_fcc 0x5 1
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set_fcc 0x5 1
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fcbgtlr fcc1,1,1
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fcbgtlr fcc1,1,1
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set_fcc 0x6 2
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set_fcc 0x6 2
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fcbgtlr fcc2,1,2
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fcbgtlr fcc2,1,2
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set_fcc 0x7 3
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set_fcc 0x7 3
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fcbgtlr fcc3,1,3
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fcbgtlr fcc3,1,3
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set_fcc 0x8 0
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set_fcc 0x8 0
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fcbgtlr fcc0,1,0
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fcbgtlr fcc0,1,0
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set_fcc 0x9 1
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set_fcc 0x9 1
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fcbgtlr fcc1,1,1
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fcbgtlr fcc1,1,1
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set_fcc 0xa 2
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set_fcc 0xa 2
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fcbgtlr fcc2,1,2
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fcbgtlr fcc2,1,2
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set_fcc 0xb 3
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set_fcc 0xb 3
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fcbgtlr fcc3,1,3
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fcbgtlr fcc3,1,3
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set_fcc 0xc 0
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set_fcc 0xc 0
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fcbgtlr fcc0,1,0
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fcbgtlr fcc0,1,0
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set_fcc 0xd 1
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set_fcc 0xd 1
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fcbgtlr fcc1,1,1
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fcbgtlr fcc1,1,1
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set_fcc 0xe 2
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set_fcc 0xe 2
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fcbgtlr fcc2,1,2
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fcbgtlr fcc2,1,2
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set_fcc 0xf 3
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set_fcc 0xf 3
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fcbgtlr fcc3,1,3
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fcbgtlr fcc3,1,3
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; ccond is false
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; ccond is false
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0x0 0
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set_fcc 0x0 0
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fcbgtlr fcc0,0,0
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fcbgtlr fcc0,0,0
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0x1 1
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set_fcc 0x1 1
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fcbgtlr fcc1,0,1
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fcbgtlr fcc1,0,1
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0x2 2
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set_fcc 0x2 2
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fcbgtlr fcc2,0,2
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fcbgtlr fcc2,0,2
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0x3 3
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set_fcc 0x3 3
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fcbgtlr fcc3,0,3
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fcbgtlr fcc3,0,3
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0x4 0
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set_fcc 0x4 0
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fcbgtlr fcc0,0,0
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fcbgtlr fcc0,0,0
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0x5 1
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set_fcc 0x5 1
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fcbgtlr fcc1,0,1
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fcbgtlr fcc1,0,1
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0x6 2
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set_fcc 0x6 2
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fcbgtlr fcc2,0,2
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fcbgtlr fcc2,0,2
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0x7 3
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set_fcc 0x7 3
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fcbgtlr fcc3,0,3
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fcbgtlr fcc3,0,3
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0x8 0
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set_fcc 0x8 0
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fcbgtlr fcc0,0,0
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fcbgtlr fcc0,0,0
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0x9 1
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set_fcc 0x9 1
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fcbgtlr fcc1,0,1
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fcbgtlr fcc1,0,1
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0xa 2
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set_fcc 0xa 2
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fcbgtlr fcc2,0,2
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fcbgtlr fcc2,0,2
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0xb 3
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set_fcc 0xb 3
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fcbgtlr fcc3,0,3
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fcbgtlr fcc3,0,3
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0xc 0
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set_fcc 0xc 0
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fcbgtlr fcc0,0,0
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fcbgtlr fcc0,0,0
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0xd 1
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set_fcc 0xd 1
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fcbgtlr fcc1,0,1
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fcbgtlr fcc1,0,1
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0xe 2
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set_fcc 0xe 2
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fcbgtlr fcc2,0,2
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fcbgtlr fcc2,0,2
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set_spr_immed 1,lcr
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set_spr_immed 1,lcr
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set_fcc 0xf 3
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set_fcc 0xf 3
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fcbgtlr fcc3,0,3
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fcbgtlr fcc3,0,3
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pass
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pass
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bad:
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bad:
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fail
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fail
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