# frv testcase for fckeq $FCCi,$CCj_float
|
# frv testcase for fckeq $FCCi,$CCj_float
|
# mach: all
|
# mach: all
|
|
|
.include "testutils.inc"
|
.include "testutils.inc"
|
|
|
start
|
start
|
|
|
.global fckeq
|
.global fckeq
|
fckeq:
|
fckeq:
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0x0 0
|
set_fcc 0x0 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1b9b,cccr
|
test_spr_immed 0x1b9b,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0x1 0
|
set_fcc 0x1 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1b9b,cccr
|
test_spr_immed 0x1b9b,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0x2 0
|
set_fcc 0x2 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1b9b,cccr
|
test_spr_immed 0x1b9b,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0x3 0
|
set_fcc 0x3 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1b9b,cccr
|
test_spr_immed 0x1b9b,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0x4 0
|
set_fcc 0x4 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1b9b,cccr
|
test_spr_immed 0x1b9b,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0x5 0
|
set_fcc 0x5 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1b9b,cccr
|
test_spr_immed 0x1b9b,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0x6 0
|
set_fcc 0x6 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1b9b,cccr
|
test_spr_immed 0x1b9b,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0x7 0
|
set_fcc 0x7 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1b9b,cccr
|
test_spr_immed 0x1b9b,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0x8 0
|
set_fcc 0x8 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1bdb,cccr
|
test_spr_immed 0x1bdb,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0x9 0
|
set_fcc 0x9 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1bdb,cccr
|
test_spr_immed 0x1bdb,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0xa 0
|
set_fcc 0xa 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1bdb,cccr
|
test_spr_immed 0x1bdb,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0xb 0
|
set_fcc 0xb 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1bdb,cccr
|
test_spr_immed 0x1bdb,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0xc 0
|
set_fcc 0xc 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1bdb,cccr
|
test_spr_immed 0x1bdb,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0xd 0
|
set_fcc 0xd 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1bdb,cccr
|
test_spr_immed 0x1bdb,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0xe 0
|
set_fcc 0xe 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1bdb,cccr
|
test_spr_immed 0x1bdb,cccr
|
|
|
set_spr_immed 0x1b1b,cccr
|
set_spr_immed 0x1b1b,cccr
|
set_fcc 0xf 0
|
set_fcc 0xf 0
|
fckeq fcc0,cc3
|
fckeq fcc0,cc3
|
test_spr_immed 0x1bdb,cccr
|
test_spr_immed 0x1bdb,cccr
|
|
|
pass
|
pass
|
|
|
