# frv testcase for fckue $FCCi,$CCj_float
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# frv testcase for fckue $FCCi,$CCj_float
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# mach: all
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# mach: all
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global fckue
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.global fckue
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fckue:
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fckue:
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0x0 0
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set_fcc 0x0 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1b9b,cccr
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test_spr_immed 0x1b9b,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0x1 0
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set_fcc 0x1 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1bdb,cccr
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0x2 0
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set_fcc 0x2 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1b9b,cccr
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test_spr_immed 0x1b9b,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0x3 0
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set_fcc 0x3 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1bdb,cccr
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0x4 0
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set_fcc 0x4 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1b9b,cccr
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test_spr_immed 0x1b9b,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0x5 0
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set_fcc 0x5 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1bdb,cccr
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0x6 0
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set_fcc 0x6 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1b9b,cccr
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test_spr_immed 0x1b9b,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0x7 0
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set_fcc 0x7 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1bdb,cccr
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0x8 0
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set_fcc 0x8 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1bdb,cccr
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0x9 0
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set_fcc 0x9 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1bdb,cccr
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0xa 0
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set_fcc 0xa 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1bdb,cccr
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0xb 0
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set_fcc 0xb 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1bdb,cccr
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0xc 0
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set_fcc 0xc 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1bdb,cccr
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0xd 0
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set_fcc 0xd 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1bdb,cccr
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0xe 0
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set_fcc 0xe 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1bdb,cccr
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b1b,cccr
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set_fcc 0xf 0
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set_fcc 0xf 0
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fckue fcc0,cc3
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fckue fcc0,cc3
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test_spr_immed 0x1bdb,cccr
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test_spr_immed 0x1bdb,cccr
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pass
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pass
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