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[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [frv/] [fr400/] [movsg.cgs] - Diff between revs 24 and 33

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Rev 24 Rev 33
# frv testcase for movsg iacc0[hl],$GRj
# frv testcase for movsg iacc0[hl],$GRj
# mach: fr400
# mach: fr400
        .include "../testutils.inc"
        .include "../testutils.inc"
        start
        start
        .global movsg
        .global movsg
Iacc0h:
Iacc0h:
        set_spr_limmed  0xdead,0xbeef,iacc0h
        set_spr_limmed  0xdead,0xbeef,iacc0h
        set_gr_limmed   0,0,gr8
        set_gr_limmed   0,0,gr8
        movsg iacc0h,gr8
        movsg iacc0h,gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_spr_limmed 0xdead,0xbeef,iacc0h
        test_spr_limmed 0xdead,0xbeef,iacc0h
Iacc0l:
Iacc0l:
        set_spr_limmed  0xdead,0xbeef,iacc0l
        set_spr_limmed  0xdead,0xbeef,iacc0l
        set_gr_limmed   0,0,gr8
        set_gr_limmed   0,0,gr8
        movsg iacc0l,gr8
        movsg iacc0l,gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_spr_limmed 0xdead,0xbeef,iacc0l
        test_spr_limmed 0xdead,0xbeef,iacc0l
Spr280:
Spr280:
        set_spr_limmed  0xdead,0xbeef,spr[280]
        set_spr_limmed  0xdead,0xbeef,spr[280]
        set_gr_limmed   0,0,gr8
        set_gr_limmed   0,0,gr8
        movsg spr[280],gr8
        movsg spr[280],gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_spr_limmed 0xdead,0xbeef,spr[280]
        test_spr_limmed 0xdead,0xbeef,spr[280]
Spr281:
Spr281:
        set_spr_limmed  0xdead,0xbeef,spr[281]
        set_spr_limmed  0xdead,0xbeef,spr[281]
        set_gr_limmed   0,0,gr8
        set_gr_limmed   0,0,gr8
        movsg spr[281],gr8
        movsg spr[281],gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_spr_limmed 0xdead,0xbeef,spr[281]
        test_spr_limmed 0xdead,0xbeef,spr[281]
Iacc0h_spr280:
Iacc0h_spr280:
        set_spr_limmed  0xdead,0xbeef,spr[280]
        set_spr_limmed  0xdead,0xbeef,spr[280]
        set_spr_limmed  0xdead,0xbeef,iacc0h
        set_spr_limmed  0xdead,0xbeef,iacc0h
        set_gr_limmed   0,0,gr8
        set_gr_limmed   0,0,gr8
        movsg iacc0h,gr8
        movsg iacc0h,gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_spr_limmed 0xdead,0xbeef,spr[280]
        test_spr_limmed 0xdead,0xbeef,spr[280]
Iacc0l_spr281:
Iacc0l_spr281:
        set_spr_limmed  0xdead,0xbeef,spr[281]
        set_spr_limmed  0xdead,0xbeef,spr[281]
        set_spr_limmed  0xdead,0xbeef,iacc0l
        set_spr_limmed  0xdead,0xbeef,iacc0l
        set_gr_limmed   0,0,gr8
        set_gr_limmed   0,0,gr8
        movsg iacc0l,gr8
        movsg iacc0l,gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_spr_limmed 0xdead,0xbeef,spr[281]
        test_spr_limmed 0xdead,0xbeef,spr[281]
Spr280_iacc0h:
Spr280_iacc0h:
        set_spr_limmed  0xdead,0xbeef,spr[280]
        set_spr_limmed  0xdead,0xbeef,spr[280]
        set_spr_limmed  0xdead,0xbeef,iacc0h
        set_spr_limmed  0xdead,0xbeef,iacc0h
        set_gr_limmed   0,0,gr8
        set_gr_limmed   0,0,gr8
        movsg spr[280],gr8
        movsg spr[280],gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_spr_limmed 0xdead,0xbeef,iacc0h
        test_spr_limmed 0xdead,0xbeef,iacc0h
Spr281_iacc0l:
Spr281_iacc0l:
        set_spr_limmed  0xdead,0xbeef,spr[281]
        set_spr_limmed  0xdead,0xbeef,spr[281]
        set_spr_limmed  0xdead,0xbeef,iacc0l
        set_spr_limmed  0xdead,0xbeef,iacc0l
        set_gr_limmed   0,0,gr8
        set_gr_limmed   0,0,gr8
        movsg spr[281],gr8
        movsg spr[281],gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_gr_limmed  0xdead,0xbeef,gr8
        test_spr_limmed 0xdead,0xbeef,iacc0l
        test_spr_limmed 0xdead,0xbeef,iacc0l
        pass
        pass
 
 

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