# frv testcase for smu $GRi,$GRj
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# frv testcase for smu $GRi,$GRj
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# mach: fr405 fr450
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# mach: fr405 fr450
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.include "../testutils.inc"
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.include "../testutils.inc"
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start
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start
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.global smu
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.global smu
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smu1:
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smu1:
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; Positive operands
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; Positive operands
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set_gr_immed 3,gr7 ; multiply small numbers
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set_gr_immed 3,gr7 ; multiply small numbers
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set_gr_immed 2,gr8
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set_gr_immed 2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed 3,gr7
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test_gr_immed 3,gr7
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test_gr_immed 2,gr8
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test_gr_immed 2,gr8
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test_spr_immed 6,iacc0l
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test_spr_immed 6,iacc0l
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test_spr_immed 0,iacc0h
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test_spr_immed 0,iacc0h
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smu2:
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smu2:
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set_gr_immed 1,gr7 ; multiply by 1
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set_gr_immed 1,gr7 ; multiply by 1
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set_gr_immed 2,gr8
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set_gr_immed 2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed 1,gr7
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test_gr_immed 1,gr7
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test_gr_immed 2,gr8
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test_gr_immed 2,gr8
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test_spr_immed 2,iacc0l
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test_spr_immed 2,iacc0l
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test_spr_immed 0,iacc0h
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test_spr_immed 0,iacc0h
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smu3:
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smu3:
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set_gr_immed 2,gr7 ; multiply by 1
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set_gr_immed 2,gr7 ; multiply by 1
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set_gr_immed 1,gr8
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set_gr_immed 1,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed 1,gr8
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test_gr_immed 1,gr8
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test_gr_immed 2,gr7
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test_gr_immed 2,gr7
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test_spr_immed 2,iacc0l
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test_spr_immed 2,iacc0l
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test_spr_immed 0,iacc0h
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test_spr_immed 0,iacc0h
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smu4:
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smu4:
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set_gr_immed 0,gr7 ; multiply by 0
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set_gr_immed 0,gr7 ; multiply by 0
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set_gr_immed 2,gr8
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set_gr_immed 2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed 2,gr8
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test_gr_immed 2,gr8
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test_gr_immed 0,gr7
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test_gr_immed 0,gr7
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test_spr_immed 0,iacc0l
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test_spr_immed 0,iacc0l
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test_spr_immed 0,iacc0h
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test_spr_immed 0,iacc0h
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smu5:
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smu5:
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set_gr_immed 2,gr7 ; multiply by 0
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set_gr_immed 2,gr7 ; multiply by 0
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set_gr_immed 0,gr8
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set_gr_immed 0,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed 0,gr8
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test_gr_immed 0,gr8
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test_gr_immed 2,gr7
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test_gr_immed 2,gr7
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test_spr_immed 0,iacc0l
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test_spr_immed 0,iacc0l
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test_spr_immed 0,iacc0h
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test_spr_immed 0,iacc0h
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smu6:
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smu6:
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set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result
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set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result
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set_gr_immed 2,gr8
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set_gr_immed 2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed 2,gr8
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test_gr_immed 2,gr8
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test_gr_limmed 0x3fff,0xffff,gr7
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test_gr_limmed 0x3fff,0xffff,gr7
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test_spr_limmed 0x7fff,0xfffe,iacc0l
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test_spr_limmed 0x7fff,0xfffe,iacc0l
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test_spr_immed 0,iacc0h
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test_spr_immed 0,iacc0h
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smu7:
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smu7:
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set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
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set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
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set_gr_immed 2,gr8
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set_gr_immed 2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed 2,gr8
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test_gr_immed 2,gr8
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test_gr_limmed 0x4000,0x0000,gr7
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test_gr_limmed 0x4000,0x0000,gr7
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test_spr_limmed 0x8000,0x0000,iacc0l
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test_spr_limmed 0x8000,0x0000,iacc0l
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test_spr_immed 0,iacc0h
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test_spr_immed 0,iacc0h
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smu8:
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smu8:
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set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
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set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
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set_gr_immed 4,gr8
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set_gr_immed 4,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed 4,gr8
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test_gr_immed 4,gr8
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test_gr_limmed 0x4000,0x0000,gr7
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test_gr_limmed 0x4000,0x0000,gr7
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test_spr_immed 0,iacc0l
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test_spr_immed 0,iacc0l
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test_spr_immed 1,iacc0h
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test_spr_immed 1,iacc0h
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smu9:
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smu9:
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set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result
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set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result
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set_gr_limmed 0x7fff,0xffff,gr8
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set_gr_limmed 0x7fff,0xffff,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_limmed 0x7fff,0xffff,gr8
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test_gr_limmed 0x7fff,0xffff,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_immed 0x00000001,iacc0l
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test_spr_immed 0x00000001,iacc0l
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test_spr_limmed 0x3fff,0xffff,iacc0h
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test_spr_limmed 0x3fff,0xffff,iacc0h
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smu10:
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smu10:
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; Mixed operands
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; Mixed operands
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set_gr_immed -3,gr7 ; multiply small numbers
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set_gr_immed -3,gr7 ; multiply small numbers
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set_gr_immed 2,gr8
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set_gr_immed 2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed 2,gr8
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test_gr_immed 2,gr8
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test_gr_immed -3,gr7
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test_gr_immed -3,gr7
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test_spr_immed -6,iacc0l
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test_spr_immed -6,iacc0l
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test_spr_immed -1,iacc0h
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test_spr_immed -1,iacc0h
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smu11:
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smu11:
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set_gr_immed 3,gr7 ; multiply small numbers
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set_gr_immed 3,gr7 ; multiply small numbers
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set_gr_immed -2,gr8
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set_gr_immed -2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -2,gr8
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test_gr_immed 3,gr7
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test_gr_immed 3,gr7
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test_spr_immed -6,iacc0l
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test_spr_immed -6,iacc0l
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test_spr_immed -1,iacc0h
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test_spr_immed -1,iacc0h
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smu12:
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smu12:
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set_gr_immed 1,gr7 ; multiply by 1
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set_gr_immed 1,gr7 ; multiply by 1
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set_gr_immed -2,gr8
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set_gr_immed -2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -2,gr8
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test_gr_immed 1,gr7
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test_gr_immed 1,gr7
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test_spr_immed -2,iacc0l
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test_spr_immed -2,iacc0l
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test_spr_immed -1,iacc0h
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test_spr_immed -1,iacc0h
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smu13:
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smu13:
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set_gr_immed -2,gr7 ; multiply by 1
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set_gr_immed -2,gr7 ; multiply by 1
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set_gr_immed 1,gr8
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set_gr_immed 1,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed 1,gr8
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test_gr_immed 1,gr8
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test_gr_immed -2,gr7
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test_gr_immed -2,gr7
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test_spr_immed -2,iacc0l
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test_spr_immed -2,iacc0l
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test_spr_immed -1,iacc0h
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test_spr_immed -1,iacc0h
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smu14:
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smu14:
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set_gr_immed 0,gr7 ; multiply by 0
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set_gr_immed 0,gr7 ; multiply by 0
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set_gr_immed -2,gr8
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set_gr_immed -2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -2,gr8
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test_gr_immed 0,gr7
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test_gr_immed 0,gr7
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test_spr_immed 0,iacc0l
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test_spr_immed 0,iacc0l
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test_spr_immed 0,iacc0h
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test_spr_immed 0,iacc0h
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smu15:
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smu15:
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set_gr_immed -2,gr7 ; multiply by 0
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set_gr_immed -2,gr7 ; multiply by 0
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set_gr_immed 0,gr8
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set_gr_immed 0,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed 0,gr8
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test_gr_immed 0,gr8
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test_gr_immed -2,gr7
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test_gr_immed -2,gr7
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test_spr_immed 0,iacc0l
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test_spr_immed 0,iacc0l
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test_spr_immed 0,iacc0h
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test_spr_immed 0,iacc0h
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smu16:
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smu16:
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set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result
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set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result
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set_gr_immed -2,gr8
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set_gr_immed -2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -2,gr8
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test_gr_limmed 0x2000,0x0001,gr7
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test_gr_limmed 0x2000,0x0001,gr7
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test_spr_limmed 0xbfff,0xfffe,iacc0l
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test_spr_limmed 0xbfff,0xfffe,iacc0l
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test_spr_limmed 0xffff,0xffff,iacc0h
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test_spr_limmed 0xffff,0xffff,iacc0h
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smu17:
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smu17:
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set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
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set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
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set_gr_immed -2,gr8
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set_gr_immed -2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -2,gr8
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test_gr_limmed 0x4000,0x0000,gr7
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test_gr_limmed 0x4000,0x0000,gr7
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test_spr_limmed 0x8000,0x0000,iacc0l
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test_spr_limmed 0x8000,0x0000,iacc0l
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test_spr_limmed 0xffff,0xffff,iacc0h
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test_spr_limmed 0xffff,0xffff,iacc0h
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smu18:
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smu18:
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set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result
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set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result
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set_gr_immed -2,gr8
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set_gr_immed -2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -2,gr8
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test_gr_limmed 0x4000,0x0001,gr7
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test_gr_limmed 0x4000,0x0001,gr7
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test_spr_limmed 0x7fff,0xfffe,iacc0l
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test_spr_limmed 0x7fff,0xfffe,iacc0l
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test_spr_limmed 0xffff,0xffff,iacc0h
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test_spr_limmed 0xffff,0xffff,iacc0h
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smu19:
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smu19:
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set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
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set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
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set_gr_immed -4,gr8
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set_gr_immed -4,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed -4,gr8
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test_gr_immed -4,gr8
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test_gr_limmed 0x4000,0x0000,gr7
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test_gr_limmed 0x4000,0x0000,gr7
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test_spr_limmed 0x0000,0x0000,iacc0l
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test_spr_limmed 0x0000,0x0000,iacc0l
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test_spr_limmed 0xffff,0xffff,iacc0h
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test_spr_limmed 0xffff,0xffff,iacc0h
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smu20:
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smu20:
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set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result
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set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result
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set_gr_limmed 0x8000,0x0000,gr8
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set_gr_limmed 0x8000,0x0000,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_limmed 0x8000,0x0000,gr8
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test_gr_limmed 0x8000,0x0000,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0x8000,0x0000,iacc0l
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test_spr_limmed 0x8000,0x0000,iacc0l
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test_spr_limmed 0xc000,0x0000,iacc0h
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test_spr_limmed 0xc000,0x0000,iacc0h
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smu21:
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smu21:
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; Negative operands
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; Negative operands
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set_gr_immed -3,gr7 ; multiply small numbers
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set_gr_immed -3,gr7 ; multiply small numbers
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set_gr_immed -2,gr8
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set_gr_immed -2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -2,gr8
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test_gr_immed -3,gr7
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test_gr_immed -3,gr7
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test_spr_immed 6,iacc0l
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test_spr_immed 6,iacc0l
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test_spr_immed 0,iacc0h
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test_spr_immed 0,iacc0h
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smu22:
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smu22:
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set_gr_immed -1,gr7 ; multiply by 1
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set_gr_immed -1,gr7 ; multiply by 1
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set_gr_immed -2,gr8
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set_gr_immed -2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -2,gr8
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test_gr_immed -1,gr7
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test_gr_immed -1,gr7
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test_spr_immed 2,iacc0l
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test_spr_immed 2,iacc0l
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test_spr_immed 0,iacc0h
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test_spr_immed 0,iacc0h
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smu23:
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smu23:
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set_gr_immed -2,gr7 ; multiply by 1
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set_gr_immed -2,gr7 ; multiply by 1
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set_gr_immed -1,gr8
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set_gr_immed -1,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed -1,gr8
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test_gr_immed -1,gr8
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test_gr_immed -2,gr7
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test_gr_immed -2,gr7
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test_spr_immed 2,iacc0l
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test_spr_immed 2,iacc0l
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test_spr_immed 0,iacc0h
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test_spr_immed 0,iacc0h
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smu24:
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smu24:
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set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result
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set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result
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set_gr_immed -2,gr8
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set_gr_immed -2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -2,gr8
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test_gr_limmed 0xc000,0x0001,gr7
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test_gr_limmed 0xc000,0x0001,gr7
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test_spr_limmed 0x7fff,0xfffe,iacc0l
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test_spr_limmed 0x7fff,0xfffe,iacc0l
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test_spr_immed 0,iacc0h
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test_spr_immed 0,iacc0h
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smu25:
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smu25:
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set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result
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set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result
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set_gr_immed -2,gr8
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set_gr_immed -2,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -2,gr8
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test_gr_limmed 0xc000,0x0000,gr7
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test_gr_limmed 0xc000,0x0000,gr7
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test_spr_limmed 0x8000,0x0000,iacc0l
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test_spr_limmed 0x8000,0x0000,iacc0l
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test_spr_immed 0,iacc0h
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test_spr_immed 0,iacc0h
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smu26:
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smu26:
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set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result
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set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result
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set_gr_immed -4,gr8
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set_gr_immed -4,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_immed -4,gr8
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test_gr_immed -4,gr8
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test_gr_limmed 0xc000,0x0000,gr7
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test_gr_limmed 0xc000,0x0000,gr7
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test_spr_immed 0x00000000,iacc0l
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test_spr_immed 0x00000000,iacc0l
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test_spr_immed 1,iacc0h
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test_spr_immed 1,iacc0h
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smu27:
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smu27:
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set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result
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set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result
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set_gr_limmed 0x8000,0x0001,gr8
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set_gr_limmed 0x8000,0x0001,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_limmed 0x8000,0x0001,gr8
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test_gr_limmed 0x8000,0x0001,gr8
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test_gr_limmed 0x8000,0x0001,gr7
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test_gr_limmed 0x8000,0x0001,gr7
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test_spr_immed 0x00000001,iacc0l
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test_spr_immed 0x00000001,iacc0l
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test_spr_limmed 0x3fff,0xffff,iacc0h
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test_spr_limmed 0x3fff,0xffff,iacc0h
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smu28:
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smu28:
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set_gr_limmed 0x8000,0x0000,gr7 ; max positive result
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set_gr_limmed 0x8000,0x0000,gr7 ; max positive result
|
set_gr_limmed 0x8000,0x0000,gr8
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set_gr_limmed 0x8000,0x0000,gr8
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smu gr7,gr8
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smu gr7,gr8
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test_gr_limmed 0x8000,0x0000,gr8
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test_gr_limmed 0x8000,0x0000,gr8
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test_gr_limmed 0x8000,0x0000,gr7
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test_gr_limmed 0x8000,0x0000,gr7
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test_spr_immed 0x00000000,iacc0l
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test_spr_immed 0x00000000,iacc0l
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test_spr_limmed 0x4000,0x0000,iacc0h
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test_spr_limmed 0x4000,0x0000,iacc0h
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pass
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pass
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