# FRV testcase for dcul GRi
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# FRV testcase for dcul GRi
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# mach: all
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# mach: all
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.include "../testutils.inc"
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.include "../testutils.inc"
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start
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start
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.global dcul
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.global dcul
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dcul:
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dcul:
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or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode
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or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode
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; preload and lock all the lines in set 0 of the data cache
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; preload and lock all the lines in set 0 of the data cache
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set_gr_immed 0x70000,gr10
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set_gr_immed 0x70000,gr10
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lock_data_cache gr10
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lock_data_cache gr10
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set_mem_immed 0x11111111,gr10
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set_mem_immed 0x11111111,gr10
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test_mem_immed 0x11111111,gr10
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test_mem_immed 0x11111111,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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set_gr_immed 1,gr11
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set_gr_immed 1,gr11
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lock_data_cache gr10
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lock_data_cache gr10
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set_mem_immed 0x22222222,gr10
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set_mem_immed 0x22222222,gr10
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test_mem_immed 0x22222222,gr10
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test_mem_immed 0x22222222,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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set_gr_immed 63,gr11
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set_gr_immed 63,gr11
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lock_data_cache gr10
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lock_data_cache gr10
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set_mem_immed 0x33333333,gr10
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set_mem_immed 0x33333333,gr10
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test_mem_immed 0x33333333,gr10
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test_mem_immed 0x33333333,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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set_gr_immed 64,gr11
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set_gr_immed 64,gr11
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lock_data_cache gr10
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lock_data_cache gr10
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set_mem_immed 0x44444444,gr10
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set_mem_immed 0x44444444,gr10
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test_mem_immed 0x44444444,gr10
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test_mem_immed 0x44444444,gr10
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; Now write to another address which should be in the same set
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; Now write to another address which should be in the same set
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; the write should go through to memory, since all the lines in the
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; the write should go through to memory, since all the lines in the
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; set are locked
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; set are locked
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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set_mem_immed 0xdeadbeef,gr10
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set_mem_immed 0xdeadbeef,gr10
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test_mem_immed 0xdeadbeef,gr10
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test_mem_immed 0xdeadbeef,gr10
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; Invalidate the data cache. Only the last value stored should have made
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; Invalidate the data cache. Only the last value stored should have made
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; it through to memory
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; it through to memory
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set_gr_immed 0x70000,gr10
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set_gr_immed 0x70000,gr10
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invalidate_data_cache gr10
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invalidate_data_cache gr10
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test_mem_immed 0,gr10
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test_mem_immed 0,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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invalidate_data_cache gr10
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invalidate_data_cache gr10
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test_mem_immed 0,gr10
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test_mem_immed 0,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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invalidate_data_cache gr10
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invalidate_data_cache gr10
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test_mem_immed 0,gr10
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test_mem_immed 0,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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invalidate_data_cache gr10
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invalidate_data_cache gr10
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test_mem_immed 0,gr10
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test_mem_immed 0,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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invalidate_data_cache gr10
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invalidate_data_cache gr10
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test_mem_immed 0xdeadbeef,gr10
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test_mem_immed 0xdeadbeef,gr10
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; Now preload load and lock all the lines in set 0 of the data cache
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; Now preload load and lock all the lines in set 0 of the data cache
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; again
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; again
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set_gr_immed 0x70000,gr10
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set_gr_immed 0x70000,gr10
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lock_data_cache gr10
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lock_data_cache gr10
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set_mem_immed 0x11111111,gr10
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set_mem_immed 0x11111111,gr10
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test_mem_immed 0x11111111,gr10
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test_mem_immed 0x11111111,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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set_gr_immed 1,gr11
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set_gr_immed 1,gr11
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lock_data_cache gr10
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lock_data_cache gr10
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set_mem_immed 0x22222222,gr10
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set_mem_immed 0x22222222,gr10
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test_mem_immed 0x22222222,gr10
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test_mem_immed 0x22222222,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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set_gr_immed 63,gr11
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set_gr_immed 63,gr11
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lock_data_cache gr10
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lock_data_cache gr10
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set_mem_immed 0x33333333,gr10
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set_mem_immed 0x33333333,gr10
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test_mem_immed 0x33333333,gr10
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test_mem_immed 0x33333333,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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set_gr_immed 64,gr11
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set_gr_immed 64,gr11
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lock_data_cache gr10
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lock_data_cache gr10
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set_mem_immed 0x44444444,gr10
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set_mem_immed 0x44444444,gr10
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test_mem_immed 0x44444444,gr10
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test_mem_immed 0x44444444,gr10
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; unlock one line
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; unlock one line
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set_gr_immed 0x78000,gr10
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set_gr_immed 0x78000,gr10
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dcul gr10
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dcul gr10
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; Now write to another address which should be in the same set.
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; Now write to another address which should be in the same set.
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set_gr_immed 0x7a000,gr10
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set_gr_immed 0x7a000,gr10
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set_mem_immed 0xbeefdead,gr10
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set_mem_immed 0xbeefdead,gr10
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; All of the stored values should be retrievable
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; All of the stored values should be retrievable
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set_gr_immed 0x70000,gr10
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set_gr_immed 0x70000,gr10
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test_mem_immed 0x11111111,gr10
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test_mem_immed 0x11111111,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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test_mem_immed 0x22222222,gr10
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test_mem_immed 0x22222222,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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test_mem_immed 0x33333333,gr10
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test_mem_immed 0x33333333,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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test_mem_immed 0x44444444,gr10
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test_mem_immed 0x44444444,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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test_mem_immed 0xdeadbeef,gr10
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test_mem_immed 0xdeadbeef,gr10
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inc_gr_immed 0x2000,gr10
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inc_gr_immed 0x2000,gr10
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test_mem_immed 0xbeefdead,gr10
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test_mem_immed 0xbeefdead,gr10
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pass
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pass
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