# FRV testcase for icpl GRi,GRj,lock
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# FRV testcase for icpl GRi,GRj,lock
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# mach: all
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# mach: all
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global icpl
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.global icpl
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; keep this at least 64 bytes away from doit2
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; keep this at least 64 bytes away from doit2
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bra icpl
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bra icpl
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doit1: add gr11,gr12,gr11
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doit1: add gr11,gr12,gr11
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bralr
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bralr
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icpl:
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icpl:
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or_spr_immed 0x80000000,hsr0 ; insn cache: enable
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or_spr_immed 0x80000000,hsr0 ; insn cache: enable
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and_spr_immed 0xbfffffff,hsr0 ; data cache: disable
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and_spr_immed 0xbfffffff,hsr0 ; data cache: disable
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set_gr_immed 0,gr11
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set_gr_immed 0,gr11
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set_gr_immed 1,gr12
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set_gr_immed 1,gr12
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set_gr_immed 2,gr13
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set_gr_immed 2,gr13
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set_gr_addr doit1,gr10
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set_gr_addr doit1,gr10
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icpl gr10,gr0,0 ; preload insns at doit1
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icpl gr10,gr0,0 ; preload insns at doit1
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set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11
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set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11
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set_gr_addr doit2,gr10
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set_gr_addr doit2,gr10
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set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11
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set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11
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set_spr_addr ok1,lr
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set_spr_addr ok1,lr
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bra doit1
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bra doit1
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ok1: test_gr_immed 1,gr11 ; used preloaded add of 1
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ok1: test_gr_immed 1,gr11 ; used preloaded add of 1
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set_spr_addr ok2,lr
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set_spr_addr ok2,lr
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bra doit2
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bra doit2
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ok2: test_gr_immed 3,gr11 ; used changed add of 2
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ok2: test_gr_immed 3,gr11 ; used changed add of 2
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pass
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pass
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doit2: add gr11,gr12,gr11
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doit2: add gr11,gr12,gr11
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bralr
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bralr
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