# FRV testcase
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# FRV testcase
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# mach: fr500 fr550 fr400
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# mach: fr500 fr550 fr400
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global tra
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.global tra
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tra:
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tra:
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and_spr_immed 0x3fffffff,hsr0 ; no caches enabled
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and_spr_immed 0x3fffffff,hsr0 ; no caches enabled
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and_spr_immed -4081,tbr ; clear tbr.tt
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and_spr_immed -4081,tbr ; clear tbr.tt
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set_gr_spr tbr,gr7
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set_gr_spr tbr,gr7
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inc_gr_immed 0x070,gr7 ; address of exception handler
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inc_gr_immed 0x070,gr7 ; address of exception handler
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set_bctrlr_0_0 gr7
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set_bctrlr_0_0 gr7
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inc_gr_immed 0x790,gr7 ; address of exception handler
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inc_gr_immed 0x790,gr7 ; address of exception handler
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set_bctrlr_0_0 gr7
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set_bctrlr_0_0 gr7
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set_spr_immed 128,lcr
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set_spr_immed 128,lcr
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set_psr_et 1
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set_psr_et 1
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set_spr_addr ok0,lr
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set_spr_addr ok0,lr
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set_gr_addr ill1,gr7
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set_gr_addr ill1,gr7
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set_mem_immed 0x81f80000,gr7 ; unknown opcode: 7E
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set_mem_immed 0x81f80000,gr7 ; unknown opcode: 7E
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ill1: tira gr0,0 ; should be overridden
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ill1: tira gr0,0 ; should be overridden
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ill2: nop ; also illegal, but prev has priority
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ill2: nop ; also illegal, but prev has priority
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bad0: fail
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bad0: fail
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; check interrupt
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; check interrupt
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ok0: test_spr_addr ill1,pcsr
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ok0: test_spr_addr ill1,pcsr
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test_spr_immed 1,esfr1 ; esr0 active
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test_spr_immed 1,esfr1 ; esr0 active
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test_spr_bits 0x3f,0,0xb,esr0
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test_spr_bits 0x3f,0,0xb,esr0
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movsg psr,gr28
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movsg psr,gr28
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srli gr28,28,gr28
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srli gr28,28,gr28
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subicc gr28,0x3,gr0,icc3 ; is fr550?
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subicc gr28,0x3,gr0,icc3 ; is fr550?
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beq icc3,0,no_epcr
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beq icc3,0,no_epcr
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test_spr_addr ill1,epcr0
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test_spr_addr ill1,epcr0
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no_epcr:
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no_epcr:
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pass
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pass
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