# frv testcase for sraicc $GRi,$GRj,$GRk,$ICCi_1
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# frv testcase for sraicc $GRi,$GRj,$GRk,$ICCi_1
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# mach: all
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# mach: all
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global sraicc
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.global sraicc
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sraicc:
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sraicc:
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set_gr_limmed 0x8000,0x0000,gr8
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set_gr_limmed 0x8000,0x0000,gr8
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set_icc 0x05,0 ; Set mask opposite of expected
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set_icc 0x05,0 ; Set mask opposite of expected
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sraicc gr8,0x1e0,gr8,icc0 ; Shift by 0
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sraicc gr8,0x1e0,gr8,icc0 ; Shift by 0
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test_icc 1 0 0 0 icc0
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test_icc 1 0 0 0 icc0
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test_gr_limmed 0x8000,0x0000,gr8
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test_gr_limmed 0x8000,0x0000,gr8
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set_gr_limmed 0x8000,0x0000,gr8
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set_gr_limmed 0x8000,0x0000,gr8
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set_icc 0x07,0 ; Set mask opposite of expected
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set_icc 0x07,0 ; Set mask opposite of expected
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sraicc gr8,-31,gr8,icc0 ; Shift by 1
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sraicc gr8,-31,gr8,icc0 ; Shift by 1
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test_icc 1 0 1 0 icc0
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test_icc 1 0 1 0 icc0
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test_gr_limmed 0xc000,0x0000,gr8
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test_gr_limmed 0xc000,0x0000,gr8
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set_gr_limmed 0x8000,0x0000,gr8
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set_gr_limmed 0x8000,0x0000,gr8
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set_icc 0x07,0 ; Set mask opposite of expected
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set_icc 0x07,0 ; Set mask opposite of expected
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sraicc gr8,31,gr8,icc0 ; Shift by 31
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sraicc gr8,31,gr8,icc0 ; Shift by 31
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test_icc 1 0 1 0 icc0
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test_icc 1 0 1 0 icc0
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test_gr_immed -1,gr8
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test_gr_immed -1,gr8
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set_gr_limmed 0x4000,0x0000,gr8
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set_gr_limmed 0x4000,0x0000,gr8
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set_icc 0x0a,0 ; Set mask opposite of expected
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set_icc 0x0a,0 ; Set mask opposite of expected
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sraicc gr8,31,gr8,icc0 ; clear register
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sraicc gr8,31,gr8,icc0 ; clear register
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test_icc 0 1 1 1 icc0
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test_icc 0 1 1 1 icc0
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test_gr_immed 0x00000000,gr8
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test_gr_immed 0x00000000,gr8
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pass
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pass
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