OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [frv/] [stdc.pcgs] - Diff between revs 24 and 33

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 24 Rev 33
# frv parallel testcase for stdc $CPk,@($GRi,$GRj)
# frv parallel testcase for stdc $CPk,@($GRi,$GRj)
# mach: frv
# mach: frv
        .include "testutils.inc"
        .include "testutils.inc"
        start
        start
        .global stdc
        .global stdc
stdc:
stdc:
        set_mem_limmed  0xbeef,0xdead,sp
        set_mem_limmed  0xbeef,0xdead,sp
        inc_gr_immed    -4,sp
        inc_gr_immed    -4,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_gr_immed    0,gr7
        set_gr_immed    0,gr7
        set_cpr_limmed  0xbeef,0xdead,cpr8
        set_cpr_limmed  0xbeef,0xdead,cpr8
        set_cpr_limmed  0xdead,0xbeef,cpr9
        set_cpr_limmed  0xdead,0xbeef,cpr9
        stdc            cpr8,@(sp,gr7)          ; non parallel
        stdc            cpr8,@(sp,gr7)          ; non parallel
        test_mem_limmed 0xbeef,0xdead,sp
        test_mem_limmed 0xbeef,0xdead,sp
        inc_gr_immed    4,sp
        inc_gr_immed    4,sp
        test_mem_limmed 0xdead,0xbeef,sp
        test_mem_limmed 0xdead,0xbeef,sp
        set_mem_limmed  0xbeef,0xdead,sp
        set_mem_limmed  0xbeef,0xdead,sp
        inc_gr_immed    -4,sp
        inc_gr_immed    -4,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_gr_immed    4,gr7
        set_gr_immed    4,gr7
        set_cpr_limmed  0xbeef,0xdead,cpr8
        set_cpr_limmed  0xbeef,0xdead,cpr8
        set_cpr_limmed  0xdead,0xbeef,cpr9
        set_cpr_limmed  0xdead,0xbeef,cpr9
        stdc.p          cpr8,@(sp,gr0)          ; parallel
        stdc.p          cpr8,@(sp,gr0)          ; parallel
        addi            sp,4,sp
        addi            sp,4,sp
        subi            sp,4,sp
        subi            sp,4,sp
        ldc             @(sp,gr0),cpr10
        ldc             @(sp,gr0),cpr10
        ldc             @(sp,gr7),cpr11
        ldc             @(sp,gr7),cpr11
        test_mem_limmed 0xbeef,0xdead,sp        ; memory is set
        test_mem_limmed 0xbeef,0xdead,sp        ; memory is set
        inc_gr_immed    4,sp
        inc_gr_immed    4,sp
        test_mem_limmed 0xdead,0xbeef,sp
        test_mem_limmed 0xdead,0xbeef,sp
        test_cpr_limmed 0xbeef,0xdead,cpr10
        test_cpr_limmed 0xbeef,0xdead,cpr10
        test_cpr_limmed 0xdead,0xbeef,cpr11
        test_cpr_limmed 0xdead,0xbeef,cpr11
        pass
        pass
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.