# frv testcase for udiv $GRi,$GRj,$GRk
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# frv testcase for udiv $GRi,$GRj,$GRk
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# mach: frv fr500 fr400
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# mach: frv fr500 fr400
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global udiv
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.global udiv
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udiv:
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udiv:
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; simple division 12 / 3
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; simple division 12 / 3
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set_gr_immed 0x00000003,gr2
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set_gr_immed 0x00000003,gr2
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set_gr_immed 0x0000000c,gr3
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set_gr_immed 0x0000000c,gr3
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udiv gr3,gr2,gr3
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udiv gr3,gr2,gr3
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test_gr_immed 0x00000003,gr2
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test_gr_immed 0x00000003,gr2
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test_gr_immed 0x00000004,gr3
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test_gr_immed 0x00000004,gr3
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; example 1 from udiv in the fr30 manual
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; example 1 from udiv in the fr30 manual
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set_gr_limmed 0x0123,0x4567,gr2
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set_gr_limmed 0x0123,0x4567,gr2
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set_gr_limmed 0xfedc,0xba98,gr3
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set_gr_limmed 0xfedc,0xba98,gr3
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udiv gr3,gr2,gr3
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udiv gr3,gr2,gr3
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test_gr_limmed 0x0123,0x4567,gr2
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test_gr_limmed 0x0123,0x4567,gr2
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test_gr_immed 0x000000e0,gr3
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test_gr_immed 0x000000e0,gr3
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; set up exception handler
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; set up exception handler
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set_psr_et 1
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set_psr_et 1
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and_spr_immed -4081,tbr ; clear tbr.tt
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and_spr_immed -4081,tbr ; clear tbr.tt
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set_gr_spr tbr,gr17
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set_gr_spr tbr,gr17
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inc_gr_immed 0x170,gr17 ; address of exception handler
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inc_gr_immed 0x170,gr17 ; address of exception handler
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set_bctrlr_0_0 gr17
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set_bctrlr_0_0 gr17
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set_spr_immed 128,lcr
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set_spr_immed 128,lcr
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set_gr_immed 0,gr15
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set_gr_immed 0,gr15
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; divide by zero
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; divide by zero
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set_spr_addr ok1,lr
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set_spr_addr ok1,lr
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set_gr_addr e1,gr17
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set_gr_addr e1,gr17
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e1: udiv gr1,gr0,gr2 ; divide by zero
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e1: udiv gr1,gr0,gr2 ; divide by zero
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test_gr_immed 1,gr15
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test_gr_immed 1,gr15
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pass
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pass
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ok1: ; exception handler for divide by zero
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ok1: ; exception handler for divide by zero
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test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set
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test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set
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test_spr_gr epcr0,gr17 ; return address set
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test_spr_gr epcr0,gr17 ; return address set
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test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
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test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
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test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set
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test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set
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inc_gr_immed 1,gr15
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inc_gr_immed 1,gr15
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rett 0
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rett 0
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fail
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fail
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