# Hitachi H8 testcase 'and.w'
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# Hitachi H8 testcase 'and.w'
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# mach(): h8300h h8300s h8sx
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# mach(): h8300h h8300s h8sx
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# as(h8300): --defsym sim_cpu=0
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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and_w_imm16:
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and_w_imm16:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; fixme set ccr
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;; and.w #xx:16,Rd
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;; and.w #xx:16,Rd
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and.w #0xaaaa, r0 ; Immediate 16-bit operand
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and.w #0xaaaa, r0 ; Immediate 16-bit operand
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa
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test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa
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test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa
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.endif
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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.endif
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.endif
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and_w_reg:
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and_w_reg:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; fixme set ccr
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;; and.w Rs,Rd
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;; and.w Rs,Rd
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mov.w #0xaaaa, r1
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mov.w #0xaaaa, r1
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and.w r1, r0 ; Register operand
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and.w r1, r0 ; Register operand
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa
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test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa
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test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged
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test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa
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test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa
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test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged
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test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged
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.endif
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.endif
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 6
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test_gr_a5a5 7
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test_gr_a5a5 7
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pass
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pass
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exit 0
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exit 0
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