URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gdb/] [gdb-6.8/] [gdb-6.8.openrisc-2.1/] [sim/] [testsuite/] [sim/] [h8300/] [daa.s] - Diff between revs 24 and 33

Rev 24	Rev 33
`# Hitachi H8 testcase 'daa'`	`# Hitachi H8 testcase 'daa'`
`# mach(): all`	`# mach(): all`
`# as(h8300): --defsym sim_cpu=0`	`# as(h8300): --defsym sim_cpu=0`
`# as(h8300h): --defsym sim_cpu=1`	`# as(h8300h): --defsym sim_cpu=1`
`# as(h8300s): --defsym sim_cpu=2`	`# as(h8300s): --defsym sim_cpu=2`
`# as(h8sx): --defsym sim_cpu=3`	`# as(h8sx): --defsym sim_cpu=3`
`# ld(h8300h): -m h8300helf`	`# ld(h8300h): -m h8300helf`
`# ld(h8300s): -m h8300self`	`# ld(h8300s): -m h8300self`
`# ld(h8sx): -m h8300sxelf`	`# ld(h8sx): -m h8300sxelf`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`

`daa_8:`	`daa_8:`
`set_grs_a5a5 ; Fill all general regs with a fixed pattern`	`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
`;; fixme set ccr`	`;; fixme set ccr`

`;; daa Rd`	`;; daa Rd`
`daa r0l ; register operand`	`daa r0l ; register operand`

`;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0`	`;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0`

`test_h_gr8 5 r0l`	`test_h_gr8 5 r0l`
`test_gr_a5a5 1 ; Make sure other general regs not disturbed`	`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
`test_gr_a5a5 2`	`test_gr_a5a5 2`
`test_gr_a5a5 3`	`test_gr_a5a5 3`
`test_gr_a5a5 4`	`test_gr_a5a5 4`
`test_gr_a5a5 5`	`test_gr_a5a5 5`
`test_gr_a5a5 6`	`test_gr_a5a5 6`
`test_gr_a5a5 7`	`test_gr_a5a5 7`

`pass`	`pass`

`exit 0`	`exit 0`